Time-Domain Interpolator Placement for Optical Clock Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Typical optical receivers face issues with sampling time errors and phase skews due to analog-to-digital converters (ADCs), which are difficult to address through direct clock adjustment, especially when designed by different manufacturers, and placing time-domain interpolators after frequency-domain equalizers (FDEQs) introduces complex dependencies and increased hardware requirements.
Innovation Solution
Placing time-domain interpolators immediately after ADCs before FDEQs allows for sampling time adjustment, phase skew compensation, and sampling rate changes without the filtering effects of FDEQs, enabling better clock recovery performance and reducing hardware complexity by using the same-sized Fast Fourier Transform (FFT) components across different data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If time-domain interpolators are placed after frequency-domain equalizers (FDEQs), then clock recovery can be performed, but complex dependencies are introduced and hardware requirements increase
Solution Approach 1:
The patent inverts the conventional order by placing the time-domain interpolator before the frequency-domain equalizer instead of after it. This reversal eliminates the complex dependencies that arise when interpolation is performed on already-equalized signals, simplifying the overall system architecture while maintaining clock recovery functionality
2Measurement precision
If direct adjustment of ADC clock is used for clock recovery, then sampling time errors can be corrected, but implementation becomes difficult when ADCs are from different manufacturers
Solution Approach 1:
The patent introduces a time-domain interpolator as an intermediary component that operates in the digital domain after ADC conversion. This mediator corrects sampling time errors and phase skews without requiring direct modification of the ADC clock, thereby enabling clock recovery across ADCs from different manufacturers while maintaining manufacturing ease
3Productivity
If different FFT sizes are used for different data rates, then optimal processing can be achieved, but hardware and design complexity increases
Solution Approach 1:
The patent makes the FFT component universal by using a consistent FFT size across different data rates. The time-domain interpolator adapts to different data rates while the FFT processor remains unchanged, allowing a single FFT hardware design to handle multiple data rates efficiently without requiring multiple specialized FFT blocks
Data Source
AI summary
An apparatus comprising an analog-to-digital converter (ADC); a frequency-domain equalizer (FDEQ); a time-domain interpolator positioned between the ADC and the FDEQ, wherein the time domain interpolator is coupled to the ADC and the FDEQ and configured to perform a time-domain interpolation to compensate a signal sample for a plurality of ADC induced changes.