On-Chip ECC Memory Write Path for Low-Power Reliable Burst Writes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in achieving low power consumption while maintaining reliability through error-correcting code (ECC) operations, often resulting in either large data sizes that increase chip size and power consumption or inadequate overhead that compromises reliability.
Innovation Solution
A memory device configuration that includes a data latch, codeword corrector, data buffer, and codeword encoder to correct errors and optimize ECC operations, allowing for efficient writing and reading of data with reduced overhead, enabling faster burst write operations similar to SRAM or DRAM performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger data size is used to reduce ECC overhead and increase code rate, then power consumption and chip size increase, but if smaller data size is used to reduce chip size and power consumption, then ECC overhead increases and reliability requirements become harder to meet
Solution Approach 1:
The patent segments the write operation into multiple phases: receiving user data in a data buffer, reading existing data from the memory array, correcting errors in the read data using ECC, and then writing the corrected data back to the array. This segmentation allows error correction to be performed on smaller chunks of data rather than requiring the entire data set to be processed simultaneously, reducing the instantaneous power consumption and chip size requirements while maintaining reliability.
Solution Approach 2:
The patent performs preliminary error correction by reading data from the memory array and correcting errors using ECC before the actual write operation completes. The corrected data is stored in a data buffer, and only after verification is the data written to the memory array. This preliminary action ensures reliability is maintained while allowing the write operation to be optimized for lower power consumption.
2Reliability
If traditional ECC operations are used to ensure data reliability, then power consumption increases, but if power consumption is reduced, then reliability through ECC operations is compromised
Solution Approach 1:
The patent implements continuous error correction during the write operation by reading data, correcting errors, and writing corrected data in an overlapping manner. The data buffer allows the correction process to continue while the write operation progresses, ensuring continuous useful action without interruption. This maintains data reliability while optimizing energy usage by avoiding redundant correction operations.
Solution Approach 2:
The memory device performs self-correction of errors by automatically detecting and correcting errors in the read data using ECC before writing to the array. This self-service mechanism eliminates the need for external error correction operations, reducing energy loss while maintaining data reliability. The system serves itself by incorporating correction functionality within the write path.
3Productivity
If error correction is performed during write operations, then write speed decreases, but if write speed is increased, then error correction may be compromised
Solution Approach 1:
The patent implements dynamic error correction by adjusting the correction process based on the write operation status. The data buffer allows flexible timing where correction can be performed at optimal moments without strictly sequential processing. This dynamic approach enables faster burst write operations similar to SRAM or DRAM performance while maintaining error correction capability through the codeword corrector and encoder components.
Solution Approach 2:
The patent performs preliminary error correction by reading and correcting data before the write operation completes. The corrected data is prepared in advance in the data buffer, allowing the actual write to proceed at high speed without waiting for correction to finish. This preliminary action separates the correction timeline from the write timeline, enabling both high write speed and reliable error correction.
Data Source
AI summary
A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword.