Memory Controller Block-Code Decoding with XORed Parity Queues
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Solution Overview
Problem
Traditional memory controllers face bottlenecks in fast error correction due to large hardware queues and decoder sizes, which consume significant silicon area and power, limiting performance in terms of latency and power consumption.
Innovation Solution
Implementing encoder-assisted decoding for systematic linear block codes, where the memory controller only stores and processes exclusive-ORed parity bits, reducing the queue and decoder sizes, and reusing encoder logic during read operations to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional queue and decoder hardware are used to handle data from memory channels, then error correction capability is maintained, but silicon area and power consumption increase significantly
Solution Approach 1:
The patent extracts only the essential parity information from the full data stream. Instead of queuing and decoding entire data words, the system identifies and processes only the parity bits needed for error detection and correction, removing unnecessary data processing overhead and reducing hardware requirements
Solution Approach 2:
The patent segments the error correction function into two parts: (1) an encoder that generates and queues only parity bits, and (2) a simplified decoder that processes only these parity bits. This segmentation allows each component to be minimized in size while maintaining overall error correction capability
2Reliability
If large queue size is used to store data from multiple memory channels, then all data can be decoded and errors identified, but timing bottlenecks and latency increase
Solution Approach 1:
The patent extracts only the parity bits from the data stream for queuing and processing. By removing the need to queue and process entire data words, the queue depth requirement is dramatically reduced, enabling faster processing and reduced latency while maintaining error identification capability
Solution Approach 2:
The patent performs preliminary encoding to generate parity bits before data is fully received or processed. This preliminary action allows the parity information to be prepared and queued in advance, enabling the decoder to work with pre-processed, minimal data and reducing overall processing latency
3Reliability
If traditional decoder hardware processes all received data, then comprehensive error correction is achieved, but power consumption and processing time increase
Solution Approach 1:
The patent extracts only the parity bits for decoding operations, eliminating the need for the decoder to process entire data words. This extraction reduces the computational workload and power consumption of the decoder while maintaining complete error correction capability through targeted parity analysis
Solution Approach 2:
The patent applies partial action by performing decoding operations only on the essential parity information rather than all received data. This partial processing approach achieves the minimum necessary work for error correction, significantly reducing power consumption while maintaining correction completeness
Data Source
AI summary
Described herein are an apparatus, system, and method for encoder assisted decoding of linear systematic block codes. The apparatus comprises a first logic unit to receive a codeword from a memory, the codeword having a data portion and a corresponding parity portion; an encoder to encode the data portion of the received codeword and to generate a corresponding parity of the data portion of the received codeword; a second logic unit to generate a first parity portion from the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder; and a correction unit to correct the data portion of the codeword via the generated first parity portion.