Flash Memory ECC Page Recovery to Contain Write Error Propagation

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Solution Overview

Problem

Conventional semiconductor recording devices require large buffer memories to handle writing errors in multi-level flash memory systems, leading to increased physical block sizes and incompatibility with existing host apparatuses, especially when cell sharing information is unknown or not disclosed.

Innovation Solution

A semiconductor recording device configuration that uses ECC generators to distribute data across multiple physical blocks, incorporating error detection and recovery mechanisms to prevent writing error propagation without the need for large buffer memories, allowing for reliable data recovery even in cases of writing errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large buffer memory is used to handle writing errors in multi-level flash memory, then data recovery capability is improved, but device size and complexity increase

Engineering Contradiction:
Improvedata recovery capabilityVSAvoidbuffer memory size
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The physical block is divided into multiple pages (first page and second page), with each page having independent write capability. The data is segmented such that the first page can be written and partially verified before writing the second page, allowing error containment without requiring large buffer memory to hold entire block data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first page is written and verified before writing the second page. This preliminary write and verification action allows detection of writing errors early in the process, preventing error propagation to subsequent pages and eliminating the need for large buffer memory to compensate for undetected errors.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If buffer memory capacity is increased to prevent error propagation, then writing error recovery is improved, but compatibility with existing host apparatuses deteriorates

Engineering Contradiction:
Improvewriting error recoveryVSAvoidhost apparatus compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

By segmenting the write operation into page-level units with independent verification, the system achieves error recovery capability without requiring the host apparatus to support large buffer memory configurations, maintaining compatibility while improving reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The semiconductor recording device performs self-verification of written data using ECC codes and page status tracking, enabling error detection and recovery without requiring additional buffer memory resources from the host apparatus, thus maintaining compatibility.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If cell sharing information is unknown, then data distribution flexibility is improved, but error detection precision deteriorates

Engineering Contradiction:
Improvedata distribution flexibilityVSAvoiderror detection precision
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The system performs preliminary verification of the first page before writing the second page, establishing a verified baseline that enables error detection even without knowing cell sharing relationships, maintaining both flexibility and precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from ECC verification results and page status tracking to dynamically adjust write operations and error recovery strategies, enabling precise error detection without requiring advance knowledge of cell sharing information.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8533559B2Semiconductor recording device with error recovery
Publication Date: 2013.09.10 PANASONIC HOLDINGS CORP
  • US8533559B2 patent drawing
  • US8533559B2 patent drawing
  • US8533559B2 patent drawing

AI summary

An error correction code of (N+M) words is configured by adding an ECC parity of M word (M is a natural number) to N words extracted at an interval of A words with respect to data of (A*N) words (A and N are natural numbers) inputted via an interface. A data distributor distributes (N+M) words to the respective (N+M) physical blocks to record by A words. In a case where a writing error has occurred, data recorded in a cell sharing page of the page and in a page of another physical block configuring the error correction code is read. A disappearing correction is carried out to the data of the cell sharing page by using the data, and thus the data of the cell sharing page is recovered and written. In this manner, in the multi-level nonvolatile memory, an error in writing of a certain page can be prevented from propagating to a written page sharing a cell.