Hierarchical Memory Error Correction for Low-Latency Reads
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Solution Overview
Problem
As processor systems with decreasing production geometries experience increasing bit error rates due to defects and physical events, memory latency is exacerbated by the need for double bit and higher error correction mechanisms, which consume clock cycles and delay processing.
Innovation Solution
A hierarchical error correction mechanism that detects and corrects single bit errors first, using SEC-DED, and only engages double bit error correction if necessary, using DEC-TED, thereby minimizing memory latency by performing error correction only when needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double bit error correction mechanisms are engaged, then reliability is improved, but memory latency increases due to multiple clock cycles required
Solution Approach 1:
The patent segments the error correction process into hierarchical levels: first-level SEC-DED correction for common single-bit errors, and second-level DEC-TED correction for rare double-bit errors. This segmentation allows the system to handle the majority of error cases through the faster first-level correction, while reserving the slower second-level correction only for when it is actually needed, thus resolving the contradiction between reliability and latency.
Solution Approach 2:
The patent implements a dynamic error correction approach where the correction level is adjusted based on the detected error type. The system dynamically selects between first-level and second-level correction mechanisms based on whether single-bit or double-bit errors are detected, optimizing the balance between reliability and latency by applying the appropriate correction strength for each error scenario.
2Reliability
If higher order error correction techniques are used, then reliability is improved, but processing speed decreases due to additional clock cycles
Solution Approach 1:
The patent divides error correction into segmented levels where the first level (SEC-DED) handles common single-bit errors quickly, and the second level (DEC-TED) handles rare double-bit errors. This segmentation ensures that processing speed is maintained for the majority of cases while reliability is enhanced for error cases, resolving the contradiction between reliability and productivity.
Solution Approach 2:
The patent applies partial correction action by using the more intensive DEC-TED correction only when necessary (when double-bit errors are detected), rather than applying it universally. This partial application of excessive correction capability maintains processing speed for normal operations while ensuring reliability when needed.
3Reliability
If data reloads are performed for uncorrected errors, then reliability is maintained, but memory latency increases significantly
Solution Approach 1:
The patent performs preliminary error correction at two levels before data reload becomes necessary. The first-level SEC-DED and second-level DEC-TED corrections are applied proactively to detect and correct errors in-place, preventing the need for time-consuming data reloads from higher memory levels and maintaining both reliability and latency performance.
Data Source
AI summary
A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access.