LDPC Decoder Simplification for High-Speed Error Correction
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Solution Overview
Problem
Implementing low-density parity-check (LDPC) codes at high speeds, such as 40 Gb/s, is challenging due to the complexity of sum-product algorithms and the lack of regular structure in parity check matrices, making it difficult to achieve robust error correction without high implementation costs and complexity.
Innovation Solution
The method involves using reduced-complexity min-sum and a posteriori probability (APP) LDPC decoders that initialize variable-nodes based on channel reliabilities and perform attenuated check-node updates, omitting variable-node updates to reduce decoding complexity while maintaining bit-error rate performance, and employing iterative polarization quantization (IPQ) modulation for error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sum-product algorithm is used to decode LDPC codes at 40 Gb/s, then bit-error rate performance is improved, but decoding complexity and implementation cost increase significantly
Solution Approach 1:
The patent extracts and eliminates the variable-node update step from the sum-product algorithm, retaining only the check-node updates. This simplification reduces decoding complexity while maintaining acceptable bit-error rate performance through optimized check-node processing and attenuation factors.
Solution Approach 2:
The patent introduces attenuation factors to modify the check-node update equations, adjusting the parameter α to optimize performance. This parameter change allows the simplified algorithm to achieve good bit-error rate performance without requiring the full complexity of the original sum-product algorithm.
2Measurement precision
If regular LDPC decoding with variable-node updates is implemented, then decoding accuracy is improved, but storage requirements and latency increase
Solution Approach 1:
The patent removes the variable-node update mechanism entirely, eliminating the need to store and process variable-node messages. This extraction reduces storage requirements while maintaining decoding accuracy through enhanced check-node processing that compensates for the removed updates.
3Reliability
If full sum-product algorithm is used, then error correction robustness is improved, but processing speed and latency are reduced
Solution Approach 1:
By removing the variable-node update step, the patent reduces the number of processing iterations required. This extraction accelerates decoding while maintaining error correction robustness through optimized check-node updates that capture the essential error-correction functionality.
Solution Approach 2:
The patent skips the variable-node update computations entirely, rushing through only the check-node updates. This skipping mechanism reduces processing time and latency while maintaining sufficient error correction capability for high-speed operation at 40 Gb/s.
Data Source
AI summary
Methods and systems for reduced-complexity decoding of low-density parity-check (LDPC) information. An encoded input stream is received. The received stream is decoded with one or more reduced-complexity min-sum or a posteriori probability LDPC decoders. A v-node update rule in the reduced complexity decoder is omitted.