ECC Decode Verification Using Re-Encoded Parity Bits
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Solution Overview
Problem
In non-volatile data storage devices like flash memory, the increased bit error rate due to higher storage density is not effectively addressed by existing error correction coding (ECC) methods, which can fail to generate correct data even when indicating successful decoding, reducing information storage density and increasing the risk of undetected errors.
Innovation Solution
A system that uses dual ECC encoding schemes to store data with both a first and second set of parity bits, where the decoded data is re-encoded and compared to the second set to verify accuracy, allowing for error detection without adding additional redundancy like CRC check bits, thereby enhancing the error detection rate beyond the capacity of the initial ECC scheme.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC check bits are added to identify decoded data differences, then error detection capability is improved, but information storage density is reduced
Solution Approach 1:
The patent makes the existing ECC parity bits serve dual functions: error correction (original function) and error detection (new function). By re-encoding the decoded data and comparing the generated parity bits with the stored second set of parity bits, the system detects errors without adding CRC check bits, thus maintaining storage density while improving error detection capability
Solution Approach 2:
The patent combines error correction and error detection functions into a unified ECC framework. Instead of separate CRC check bits, the system merges detection capability into the existing ECC parity bit structure through a two-phase decoding process with re-encoding verification, eliminating the need for additional redundancy bits
2Reliability
If more parity bits are used to increase error correction capacity, then error correction capability is improved, but the number of bits required to store encoded data increases
Solution Approach 1:
The patent segments the error correction process into two phases: first phase uses a reduced set of parity bits for initial decoding attempts, and the second phase uses the full set of parity bits for more powerful decoding. This segmentation allows the system to achieve high error correction capacity only when necessary, reducing the average number of bits required while maintaining strong error correction capability for severe error cases
3Productivity
If first phase ECC decoding indicates success, then decoding speed is improved, but undetected errors may occur when the decoded codeword does not correspond to original data
Solution Approach 1:
The patent implements a feedback mechanism where the decoded data is re-encoded to generate computed parity bits, which are then compared with the stored second set of parity bits. This feedback loop verifies the accuracy of fast decoded results, detecting cases where the first phase decoding succeeded but produced incorrect data, thus maintaining both speed and reliability
Data Source
AI summary
A method includes initiating a decoding operation of a first portion of a codeword representation to generate a set of data bits. The first portion includes first parity bits and is associated with a first error correcting code. The method includes initiating an encoding operation of the set of data bits according to a second error correcting code to generate computed parity bits. The method includes comparing the computed parity bits to a second portion of the codeword representation to determine a number of bits that differ between the computed parity bits and the second portion of the codeword representation. The method also includes generating an indication of successful decoding in response to the number of bits that differ being less than a threshold value.