Interleaved Clock Delay Compensation for Periodic Noise

Solution Overview

Problem

Time interleaved systems, such as ADCs, are sensitive to noise at the interleaving frequency or its harmonics, which degrades their performance, and conventional noise removal techniques like digital subharmonic filters are power and area expensive.

Innovation Solution

A system that includes a master clock path, detection circuit, and actuator circuit to detect and compensate for periodic noise by adjusting the delay of the input clock, using a phase detector, demultiplexer, processing slices, and multiplexer to correct jitter and variations in supply voltage, thereby reducing subharmonic noise before it impacts system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a digital subharmonic filter is used to remove noise at the interleaving frequency, then noise removal performance is improved, but power consumption and silicon area increase

Engineering Contradiction:

Improvenoise at interleaving frequencyVSAvoidpower consumption

Core Design Contradiction:

Object-affected harmful factorsVSUse of energy by stationary object

Solution Approach 1:

The patent extracts and removes only the specific harmful subharmonic noise components at the interleving frequency and its harmonics from the clock signal, rather than using a full digital filter. This is achieved by detecting the noise characteristics and selectively eliminating them through the controllable delay element, thereby reducing power consumption and silicon area while maintaining effective noise removal.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the delay parameter of the controllable delay element in the master clock path based on detected noise characteristics. By dynamically adjusting the delay to compensate for subharmonic noise, the system achieves noise removal without requiring a power-intensive digital filter, thus resolving the contradiction between noise removal effectiveness and power consumption.

Inventive Principle:

Principle #35Parameter changes

2Object-affected harmful factors

If a digital subharmonic filter is used to remove noise at the interleaving frequency, then noise removal performance is improved, but silicon area increases

Engineering Contradiction:

Improvenoise at interleaving frequencyVSAvoidsilicon area

Core Design Contradiction:

Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent extracts and removes only the specific harmful subharmonic noise components at the interleving frequency and its harmonics from the clock signal, rather than using a full digital filter. This is achieved by detecting the noise characteristics and selectively eliminating them through the controllable delay element, thereby reducing power consumption and silicon area while maintaining effective noise removal.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the delay parameter of the controllable delay element in the master clock path based on detected noise characteristics. By dynamically adjusting the delay to compensate for subharmonic noise, the system achieves noise removal without requiring a power-intensive digital filter, thus resolving the contradiction between noise removal effectiveness and power consumption.

Inventive Principle:

Principle #35Parameter changes

3Object-affected harmful factors

If the controllable delay element adjusts delay to compensate for periodic noise, then noise compensation performance is improved, but device complexity increases

Engineering Contradiction:

Improveperiodic noise compensationVSAvoidcomplexity of clock path

Core Design Contradiction:

Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the detection circuit monitors the output clock for subharmonic noise and feeds this information back to the controllable delay element. This closed-loop feedback allows the delay element to automatically adjust and compensate for detected noise, improving compensation performance while keeping the added complexity manageable through targeted feedback rather than system-wide complexity.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The controllable delay element acts as an intermediary component between the detection circuit and the master clock path. It mediates the noise compensation by adjusting its delay parameter based on detection signals, thereby isolating the complexity of the compensation mechanism from the rest of the clock system and managing overall device complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8885671B1System for compensating for periodic noise in time interleaved system

Publication Date: 2014.11.11 KEYSIGHT TECHNOLOGIES INC

AI summary

A system for compensating for periodic noise in a time interleaved system having multiple phases of interest includes a master clock path, a detection circuit and an actuator circuit. The master clock path is configured to receive an input clock and to output an output clock, each of the input and output clocks having periodically occurring interleaving periods. Each interleaving period includes timeslots corresponding to the phases of interest of the time interleaved system. The detection circuit is configured to receive the input and output clocks for each timeslot, and to detect periodic noise in the output clock introduced by the master clock path by comparing the received input and output clocks. The actuator circuit includes a controllable delay element configured to adjust a delay of the input clock through the master clock path to compensate for the periodic noise detected by the detection circuit for each timeslot.