Dual-Mode LDPC Decoder with Shared SBD/LBD Datapaths
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Solution Overview
Problem
Current LDPC decoding algorithms, such as Standard Belief Propagation (SBD) and Layered Belief Propagation (LBD), have limitations in supporting both high and low data rate communications effectively in satellite systems, with SBD providing better error correction at low data rates and LBD converging faster at high data rates, but requiring separate hardware implementations which are inefficient in terms of power consumption, size, and flexibility.
Innovation Solution
A dual mode LDPC decoder apparatus that integrates both SBD and LBD algorithms in a single Very Large Scale Integration (VLSI) hardware module, utilizing edge RAM, LIFO/FIFO RAM, channel RAM, and parallel datapath engines, allowing for shared hardware resources and mode selection between SBD and LBD, enabling efficient operation in both high and low data rate communications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware implementations are used for SBD and LBD algorithms, then each algorithm can operate at its optimal performance, but power consumption increases and device size becomes larger
Solution Approach 1:
The patent combines both SBD and LBD decoding algorithms into a single unified hardware module that can dynamically switch between the two modes. The decoder includes a shared hardware architecture with configurable datapaths that can operate in either standard belief propagation mode or layered belief propagation mode, eliminating the need for separate hardware implementations and reducing overall power consumption while maintaining optimal performance for each algorithm.
Solution Approach 2:
The decoder is designed as a universal hardware module capable of performing both SBD and LBD algorithms through configurable control logic and shared computational resources. The hardware structure includes multiplexers and control units that can route signals and activate specific algorithmic paths based on the selected mode, allowing a single device to fulfill multiple decoding requirements without sacrificing the specialized performance advantages of either algorithm.
2Adaptability or versatility
If separate hardware implementations are used for SBD and LBD algorithms, then each algorithm can operate at its optimal performance, but the device size becomes larger
Solution Approach 1:
The patent merges the hardware implementations of SBD and LBD into a single integrated decoder unit. The unified architecture shares common computational resources, memory structures, and control logic between the two algorithms, significantly reducing the overall hardware area required while maintaining the ability to support both high data rate (LBD) and low data rate (SBD) communication scenarios.
Solution Approach 2:
The decoder employs a universal hardware design that can be configured to execute either SBD or LBD algorithms based on communication requirements. Through mode selection logic and shared functional blocks, the hardware achieves multi-functionality, supporting a wide range of data rates from 45 Msps to 225 Msps without requiring separate dedicated circuits for each algorithm, thereby minimizing device size while maximizing adaptability.
3Productivity
If separate hardware implementations are used for SBD and LBD algorithms, then each algorithm can be optimized for its specific use case, but flexibility and ease of operation decrease
Solution Approach 1:
The patent integrates both decoding algorithms into a single hardware module with unified control logic that simplifies operation. The merged design includes a mode selection interface that allows users to choose between SBD and LBD based on communication conditions, with the hardware automatically optimizing performance for the selected mode. This integration maintains high data processing rates (up to 225 Msps for LBD and 45 Msps for SBD) while reducing operational complexity compared to managing separate hardware systems.
4Speed
If LBD algorithm is used for high data rate communication, then convergence speed increases, but error correction performance at low data rates decreases
Solution Approach 1:
The decoder implements dynamic mode switching capability that allows the system to adapt between SBD and LBD algorithms based on communication conditions. The hardware includes control logic that can select the appropriate decoding mode to optimize either convergence speed (LBD for high data rates up to 225 Msps) or error correction performance (SBD for low data rates at 45 Msps), providing dynamic optimization rather than a fixed algorithmic approach.
Data Source
AI summary
An apparatus for a dual mode low density parity check (LDPC) decoder including edge random access memory (RAM), last-in-first-out/first-in-first-out (LIFO/FIFO) RAM, channel RAM, and parallel datapath engines, where the datapath engines include a standard belief propagation decoding (SBD) datapath and a layered belief propagation decoding (LBD) datapath, where the SBD datapath includes a shifter, an accumulator, multiplexers, and a g( )_sbd calculator, and where the LBD datapath includes the shifter, the multiplexers, and a g′( )_lbd calculator.