Error-Tolerant Processing Circuitry for Adaptive Voltage and Clock Control

Solution Overview

Problem

Existing data processing systems face inefficiencies in error management, particularly in detecting and repairing errors that occur during operation, which can lead to excessive time and circuit overhead, and limit the operating parameters of the system.

Innovation Solution

The system incorporates an error-resistant and error-prone portion of processing circuitry, where errors in the error-prone portion are tolerated and used to indicate the limits of operating parameters, allowing the system to continue operation without correcting these errors, thus maintaining a non-zero error rate and optimizing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error detection and repair mechanisms are implemented in data processing systems, then system reliability is improved, but time overhead and circuit complexity increase

Engineering Contradiction:

Improveerror detection and repair capabilityVSAvoidtime overhead for error repair

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The processing circuitry is divided into error-resistant portion and error-prone portion, segmenting the data processing function to handle different bits with different error tolerance levels

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the processing circuitry are assigned different error resistance characteristics - the error-resistant portion has higher error resistance while the error-prone portion has lower error resistance, matching the different error tolerance requirements of different bit positions

Inventive Principle:

Principle #3Local quality

2Reliability

If error detection and repair mechanisms are implemented in data processing systems, then system reliability is improved, but circuit complexity increases

Engineering Contradiction:

Improveerror detection and repair capabilityVSAvoidcircuit overhead for error management

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The processing circuitry is divided into error-resistant portion and error-prone portion, segmenting the data processing function to handle different bits with different error tolerance levels

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the processing circuitry are assigned different error resistance characteristics - the error-resistant portion has higher error resistance while the error-prone portion has lower error resistance, matching the different error tolerance requirements of different bit positions

Inventive Principle:

Principle #3Local quality

3Productivity

If operating parameters are pushed to higher clock frequencies and lower voltages, then productivity is improved, but error rate increases

Engineering Contradiction:

Improveclock frequency and power efficiencyVSAvoiderror rate in processing operations

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The processing circuitry is divided into error-resistant portion and error-prone portion, segmenting the data processing function to handle different bits with different error tolerance levels

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the processing circuitry are assigned different error resistance characteristics - the error-resistant portion has higher error resistance while the error-prone portion has lower error resistance, matching the different error tolerance requirements of different bit positions

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS8639975B2Error management within a data processing system

Publication Date: 2014.01.28 ARM LTD

AI summary

A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.