On-Die ECC Memory Architecture Without Extra Storage Overhead
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Solution Overview
Problem
Memory devices without error correcting codes (ECC) face reliability issues due to transient errors, while ECC systems incur increased costs and complexity from requiring additional DRAM variants and increased storage capacity, which is not feasible for lower-cost systems.
Innovation Solution
A memory device with a split bank architecture that can operate in either error check mode or non-error check mode, using a register bit to switch between modes and integrating on-die error correction logic to enable ECC generation and comparison, allowing for the use of CRC bits with read return data, thereby enhancing reliability and reducing the need for additional storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correcting codes (ECC) are used to improve reliability, then system reliability is improved, but storage requirement and cost increase
Solution Approach 1:
The memory device is divided into two separate banks: a first bank for storing data bits and a second bank for storing error check bits. This segmentation allows ECC functionality to be implemented without increasing the overall storage capacity, as each bank operates independently with its dedicated bit type.
Solution Approach 2:
Instead of adding ECC bits within the same storage dimension (increasing capacity), the patent transitions to a spatial dimension by using a separate bank structure. The error check bits are stored in a distinct bank from data bits, effectively moving the problem from a capacity constraint to a structural organization solution.
2Reliability
If additional memory devices are added to store check codes, then error correction capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines both data storage and error checking functionality into a single memory device by integrating two banks within one device package. This merging eliminates the need for separate memory devices while maintaining full ECC capability, thereby reducing overall system complexity.
Solution Approach 2:
The memory device achieves multi-functionality by enabling both data storage and error checking within a single device. The dual-bank structure allows the device to perform both functions simultaneously, eliminating the need for separate dedicated error checking devices.
3Reliability
If ECC variant DRAM is used, then error correction is enabled, but manufacturing yield decreases and cost increases
Solution Approach 1:
The patent uses two banks of the same DRAM variant type within a single device, avoiding the need for specialized ECC variant DRAM. By using homogeneous components (standard DRAM cells in both banks), manufacturing processes remain consistent with existing production lines, maintaining high yield rates.
4Reliability
If memory controllers support additional ECC pins, then ECC functionality is improved, but device complexity and space requirements increase
Solution Approach 1:
The error checking function is extracted from the data bank and placed in a separate bank, allowing independent access and management. This separation enables the memory controller to handle ECC operations without requiring additional external pins, as the error check bits are already organized in a dedicated structure within the same device.
Data Source
AI summary
Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.