Multi-Level ECC Configuration for Changing Memory Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data storage systems face challenges in dynamically adjusting error correction and detection levels due to changing hardware requirements, leading to inefficiencies and potential data loss when hardware configurations change, such as when more or less reliable memory is added.
Innovation Solution
The system allows for dynamically configurable multi-level error correction by using signals to configure check code generation and error location hardware, enabling the level of error detection and correction to be adjusted during operation to accommodate varying hardware needs without requiring additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed level of error correction and detection is used in system design, then the system can maintain stable data reliability, but the system cannot adapt when hardware changes (e.g., when more or less reliable memory is added or removed)
Solution Approach 1:
The patent implements dynamic configurability of error correction levels through control logic that can adjust the number of ECC check bits based on runtime hardware conditions. The system transitions from a static fixed-level ECC design to a dynamic multi-level ECC design where the error correction capability can be adjusted according to the actual hardware configuration, such as when memory devices are added or removed from the system.
Solution Approach 2:
The patent changes the parameter of ECC check bit allocation from a fixed value determined at design time to a variable parameter that can be adjusted at runtime. The system determines the appropriate level of error correction based on hardware reliability characteristics and available storage space, dynamically selecting the number of ECC check bits needed to match the actual hardware conditions.
2Reliability
If a higher level of error correction and detection is used, then data reliability is improved, but more storage space is required for ECC data
Solution Approach 1:
The patent enables dynamic adjustment of the ECC check bit allocation parameter based on the ratio of data bits to check bits. The system can adaptively select different ECC levels (e.g., different numbers of check bits per data block) depending on the available storage space and hardware reliability requirements, optimizing the balance between data protection and storage efficiency.
Solution Approach 2:
The patent implements a multi-level ECC approach where the system can select partial error correction capabilities rather than always using the maximum level. When hardware reliability is high or storage space is constrained, the system uses a lower level of error correction (fewer check bits). When hardware reliability is low or storage space is abundant, the system uses a higher level of error correction (more check bits), providing just enough protection without excessive overhead.
3Adaptability or versatility
If the system is designed with fixed error correction levels, then hardware costs can be controlled, but the system cannot optimize storage space when hardware configurations change
Solution Approach 1:
The patent designs a universal error correction system that can function at multiple ECC levels using the same hardware infrastructure. The control logic can dynamically select and configure different error correction capabilities within the same physical system, allowing the hardware to adapt to various storage configurations and reliability requirements without requiring separate dedicated hardware for each ECC level.
Solution Approach 2:
The patent introduces dynamic configuration capability to the error correction hardware, allowing the system to adjust its operational parameters (number of check bits, ECC level) based on runtime conditions. This dynamic approach enables the system to optimize storage space utilization when hardware configurations change, such as when memory devices are added or removed, while maintaining a relatively simple underlying hardware architecture.
Data Source
AI summary
An invention is provided for dynamically configurable error correction. The invention includes receiving a check code configuration signal, which indicates a particular level of error detection. A check code generator is configured to generate check codes based on the particular level of error detection indicated by the check code configuration signal. In addition, an error locator configuration signal is received that indicates a particular level of error addressing, and an error locator is configured to produce addresses of errors in a set of data based on the particular level of error addressing indicated by the error locator configuration signal.