NAND Flash ECC Control Using Error History for Data Retention
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Solution Overview
Problem
NAND flash memories face limitations in the number of 'Program'/ 'Erase' and 'Read' operations due to oxide film damage, leading to data retention issues and read disturbance, which can cause system failures when used as a hard disk replacement.
Innovation Solution
A memory system employing a two-step ECC process, where a high-speed L1 ECC is used for initial error correction and a high-performance L2 ECC is engaged when L1 correction fails, along with an error correction history management table to determine the appropriate ECC process based on past correction success, thereby reducing the burden on NAND flash memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash memory is used for hard disk replacement, then storage capacity and integration are improved, but data retention reliability deteriorates due to oxide film damage from repeated Program/Erase operations
Solution Approach 1:
The error correction process is segmented into two distinct stages: L1 ECC (low-density parity check) for fast correction of common errors, and L2 ECC (BCH code) for thorough correction of severe errors. This segmentation allows the system to handle different error scenarios with appropriate correction strength, preserving data reliability while maintaining performance
Solution Approach 2:
The L1 ECC correction is performed preliminarily before L2 ECC correction. By applying the faster L1 correction first and only proceeding to L2 correction when L1 fails (as indicated by error correction history), the system prepares for potential data loss by having a backup correction mechanism ready, thus maintaining reliability without always incurring the full performance penalty
2Reliability
If L2 ECC correction is always performed, then error correction reliability is improved, but processing time increases
Solution Approach 1:
The error correction strategy dynamically adapts based on error correction history information. When L1 correction succeeds, the system terminates early without invoking L2 correction. When L1 correction fails, the system transitions to L2 correction. This dynamic approach optimizes processing time by avoiding unnecessary L2 corrections while ensuring reliability when errors are present
Solution Approach 2:
The system uses error correction history information as feedback to determine the correction strategy. The history table records whether L1 correction succeeded or failed for previous operations, and this feedback guides whether to perform L2 correction in subsequent operations, creating a closed-loop control system that balances speed and reliability
3Productivity
If error correction history management is implemented, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
Instead of implementing complex real-time analysis of error patterns, the system creates a simplified copy of error correction outcomes in the error correction history table. This table stores only the essential information (whether L1 correction succeeded) without requiring complex data structures or algorithms, thus improving efficiency while minimizing the increase in device complexity
Data Source
AI summary
The embodiments include an error correction processing unit and an error correction history recording unit. The error correction processing unit performs an error correction process based on data read from a non-volatile semiconductor memory and a second-step error correction code corresponding to the data. The error correction history recording unit records error correction history indicating whether first error correction is successful through the first error correction process, in association with unit data. When error correction history of target unit data to be read indicates that correction is not successful, the second error correction process is executed without executing the first error correction process.