NAND Flash Refresh Triggering Using Error and Reset Thresholds
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Solution Overview
Problem
Existing methods for initiating refresh operations in solid-state nonvolatile memory devices, such as NAND flash, are inadequate as they either fail to address permanent bad block errors or result in excessive refresh operations due to arbitrary time-based triggers, leading to increased error probabilities.
Innovation Solution
A method that determines a block's error number and compares it to an error threshold, while also tracking the number of processor resets since the last refresh, to decide when to perform a refresh operation, thereby addressing both temporary and permanent errors effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed frequently to reduce read inability errors, then data reliability is improved, but the probability of bad block errors increases
Solution Approach 1:
The patent changes the parameters used to trigger refresh operations from fixed time intervals to dynamic thresholds based on actual error counts and reset numbers. By monitoring error numbers (comparing against error threshold) and reset numbers (comparing against reset threshold), the system adapts refresh timing to actual memory conditions, performing refreshes only when necessary rather than on a fixed schedule, thus reducing unnecessary refresh operations that could cause bad block errors while maintaining data reliability.
2Object-affected harmful factors
If a predetermined time delay is used before refresh operations, then bad block error probability is reduced, but read inability errors may persist for prolonged periods
Solution Approach 1:
The patent implements feedback mechanisms by continuously monitoring error numbers and reset numbers to dynamically determine when refresh operations should be performed. The system counts errors in memory blocks and compares them against an error threshold, while also tracking reset numbers against a reset threshold. This feedback loop allows the system to respond to actual memory conditions rather than following a predetermined schedule, ensuring refresh operations occur timely to maintain data integrity while avoiding excessive refreshes that could cause bad block errors.
3Productivity
If refresh operations are delayed too long, then fewer refresh operations are performed reducing wear, but read inability errors increase
Solution Approach 1:
The patent makes the refresh operation timing dynamic by using real-time monitoring of error numbers and reset numbers rather than fixed time intervals. The system dynamically adjusts when refresh operations occur based on actual memory conditions - performing refreshes when error thresholds are exceeded or reset thresholds are met, and avoiding refreshes when conditions are良好. This dynamic approach optimizes the balance between maintaining data retention and reducing unnecessary refresh operations.
Data Source
AI summary
A method for initiating a refresh operation of a solid-state nonvolatile memory device coupled to a processor is disclosed. The method comprises determining an error number for a block of the solid-state nonvolatile memory. The error number corresponds to an amount of error bits in a page of the block having a greatest amount of error bits. The method further comprises comparing the error number with an error threshold and determining a reset number indicating an amount of times that the processor has been reset since a previous refresh operation was performed on the block of the solid-state nonvolatile memory. The method further includes comparing the number of resets with a reset threshold and refreshing the block of the solid-state nonvolatile memory when the number of errors exceeds the error threshold and the number of resets exceeds the reset threshold.