Flash Memory Controller with Two-Stage ECC and Parity Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
BCH error correction circuits in flash storage systems are inadequate when the number of data bit errors in a data unit exceeds their error correction capacity, leading to unrecoverable data loss.
Innovation Solution
A nonvolatile memory controller with both an error correction module and a data recovery module, where the error correction module generates error correction codes for data units and corrects errors up to its capacity, and the data recovery module uses parity units to recover data units with errors beyond the correction capacity by leveraging other data units and parity information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BCH error correction circuit is used to correct data bit errors, then reliability is improved for errors within correction capacity, but data loss occurs when errors exceed correction capacity
Solution Approach 1:
The error handling process is segmented into two distinct stages: first, the BCH error correction circuit attempts to correct errors within its capacity; second, if correction fails, the data recovery module using parity units takes over to recover data. This segmentation allows the system to handle different error scenarios with appropriate methods, preventing total data loss even when BCH correction capacity is exceeded.
Solution Approach 2:
Parity units are generated and stored in advance alongside the data units before any errors occur. These parity units serve as a pre-prepared cushion or backup that can be used to recover data when BCH error correction is insufficient, thereby preventing complete data loss.
2Reliability
If only BCH error correction is implemented, then device complexity is reduced, but reliability is insufficient for high error rates
Solution Approach 1:
The system merges two error handling mechanisms: the BCH error correction circuit and the data recovery module with parity units. By combining these two approaches, the system achieves enhanced reliability for handling both small and large numbers of errors while maintaining a manageable level of complexity through modular integration.
Solution Approach 2:
The error correction system is designed with multi-functionality: the BCH circuit handles correctable errors, while the parity-based recovery module handles uncorrectable errors. This universal error handling capability allows a single system to address a wide range of error conditions without requiring entirely separate systems for each scenario.
Data Source
AI summary
A nonvolatile memory controller generates an error correction code for each data unit in a data stripe and generates a parity unit based on the data units of the data stripe. If a data unit of the data stripe has a number of data bit errors not exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller corrects any data bit errors in the data unit based on the error correction code of the data unit. Otherwise, if a data unit of the data stripe has a number of data bit error exceeding the error correction capacity of the nonvolatile memory controller, the nonvolatile memory controller recovers the data unit based on the other data units of the data stripe and the parity unit.