ECC Decoder Switching for Faster Low-Power Error Correction

Solution Overview

Problem

Conventional error detection and correction in semiconductor devices are time-consuming and consume excessive power, which hampers high-speed communication and data integrity.

Innovation Solution

A semiconductor device with an error control coding (ECC) circuit comprising a first decoder, a second decoder, and a controller, where the first decoder decodes data using a first parity and the second decoder decodes using a second parity, with the controller managing their activation based on decoding success or failure to optimize power usage and bit error rate performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional error detection and correction is used, then data integrity is ensured, but decoding time increases and power consumption increases

Engineering Contradiction:

Improvedata integrityVSAvoiddecoding time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The ECC decoding function is divided into two separate decoders: a first decoder that processes only a portion of the parity bits, and a second decoder that processes the remaining parity bits. This segmentation allows the system to achieve error correction capability while reducing the computational burden and decoding time of any single decoder, thus resolving the contradiction between data integrity and decoding time.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically selects which decoder (first or second) to activate based on the decoding outcome. If the first decoder fails to correct errors, the controller activates the second decoder as a backup. This dynamic activation strategy ensures high reliability while minimizing average decoding time and power consumption, as the full decoding capability is only engaged when necessary.

Inventive Principle:

Principle #15Dynamics

2Reliability

If conventional error detection and correction is used, then data integrity is ensured, but power consumption increases

Engineering Contradiction:

Improvedata integrityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The ECC decoding function is divided into two separate decoders: a first decoder that processes only a portion of the parity bits, and a second decoder that processes the remaining parity bits. This segmentation allows the system to achieve error correction capability while reducing the computational burden and decoding time of any single decoder, thus resolving the contradiction between data integrity and decoding time.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically selects which decoder (first or second) to activate based on the decoding outcome. If the first decoder fails to correct errors, the controller activates the second decoder as a backup. This dynamic activation strategy ensures high reliability while minimizing average decoding time and power consumption, as the full decoding capability is only engaged when necessary.

Inventive Principle:

Principle #15Dynamics

3Reliability

If multiple decoders are used to improve BER performance, then decoding accuracy improves, but device complexity increases

Engineering Contradiction:

ImproveBER performanceVSAvoiddecoder structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The ECC decoding function is divided into two separate decoders: a first decoder that processes only a portion of the parity bits, and a second decoder that processes the remaining parity bits. This segmentation allows the system to achieve error correction capability while reducing the computational burden and decoding time of any single decoder, thus resolving the contradiction between data integrity and decoding time.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Both the first and second decoders are designed with the same decoding capability and can function as primary or backup decoders. This universal design allows the system to achieve improved BER performance through multiple decoders while minimizing device complexity, as the decoders share the same structure and can be implemented using identical hardware resources.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8522124B2Semiconductor device and decoding method thereof

Publication Date: 2013.08.27 SAMSUNG ELECTRONICS CO LTD

AI summary

An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder.