Chip Individualization via Intentional Via Degradation
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Solution Overview
Problem
Existing methods for individualizing integrated circuits are sensitive to environmental variations and aging, leading to instability and potential misidentification of legitimate circuits as counterfeit.
Innovation Solution
A method is introduced to produce integrated circuits with a unique individualization region by degrading metal interconnections through an additional structuring step, where certain vias are intentionally deactivated, creating a physically unclonable function (PUF) that remains stable over time, using a wafer-level process with a set of masks for lithography patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If functional dispersions inherent in integrated circuits are used for individualization, then unique identification is achieved, but sensitivity to environmental variations and aging increases
Solution Approach 1:
The patent segments the individualization approach by separating the identification mechanism from environmental-sensitive functional parameters. Instead of relying on variations in transistor thresholds or interconnection resistances that change with temperature and aging, the invention creates a dedicated individualization region with unique structural patterns (irregular polygons, varied via densities) that are manufactured simultaneously with the functional circuits but provide stable, environment-independent identification characteristics.
Solution Approach 2:
The patent applies preliminary action by establishing the individualization region's unique structural characteristics during the initial manufacturing process, before the chip is subjected to environmental variations or aging. The random patterns of interconnection lines, vias, and polygons are created as part of the standard fabrication sequence, embedding the unique identifier permanently in the chip's physical structure from the outset, ensuring stability throughout the chip's operational life.
2Reliability
If each integrated circuit is designed uniquely, then individualization is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent applies universality by using a single, unified manufacturing process that simultaneously produces both the functional integrated circuits and their unique individualization regions. The same lithography masks, deposition techniques, and etching processes used for creating functional circuits are also used to create the individualization patterns. This multi-functional approach allows unique identification to be achieved without requiring separate manufacturing lines or additional complex processing steps.
Solution Approach 2:
The patent implements self-service by allowing the standard manufacturing process itself to generate the unique individualization patterns without requiring additional specialized equipment or complex intervention. The random variations in interconnection line routing, via placement, and polygon formation that naturally occur during normal fabrication automatically create unique identifiers for each chip, eliminating the need for separate individualization manufacturing steps.
3Measurement precision
If functional dispersions are used for individualization, then unique response times are obtained, but response stability over time decreases
Solution Approach 1:
The patent transitions from relying on temporal variations in signal propagation times to using spatial structural characteristics for individualization. Instead of measuring how long signals take to travel through functionally different circuits (which changes with temperature and aging), the invention creates and measures unique spatial patterns of interconnection lines, vias, and polygons in the individualization region. These structural dimensions provide stable, time-invariant identifiers that do not drift with environmental conditions.
Data Source
AI summary
A method for producing a plurality of chips each comprising an individualisation region, each chip comprising at least: a first and a second level of the electrical tracks, and an interconnections level comprising vias. The method includes producing on the dielectric layer covering the first level a mask having openings located in line with the electrical tracks and making the dielectric layer accessible. The method includes producing, in a region of the chip comprising the individualisation region, patterns conformed so that: first openings of the hard mask are not masked by the patterns, and second openings of the hard mask are masked by the patterns. The method includes producing via openings in the dielectric layer in line solely with the first openings. The method further includes filling in the via openings with an electrically conductive material, and producing the second level of the electrical tracks on the vias.