3D Chip Interconnection via Bonding Via Holes and Lead-Out Pads
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Solution Overview
Problem
In wafer-level packaging technology, the complexity of connection structures hinders processing speed and performance in 3D-IC devices.
Innovation Solution
A stacked chip structure is implemented, where bonding via holes from one chip are aligned and bonded to bonding pads on another chip, with a lead-out pad connecting the third chip's top wiring layer from its back surface, using dielectric and conductive materials like silicon oxide, silicon nitride, and copper, to simplify the interconnection structure and reduce length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional connection structures are used in wafer-level packaging, then device complexity increases, but processing speed and performance deteriorate
Solution Approach 1:
The connection structure is segmented into distinct functional components: bonding via holes for vertical inter-chip connections, bonding pads for electrical contact, and lead-out pads for external signal routing. This segmentation allows each component to be optimized independently, reducing overall complexity while maintaining high processing speed through specialized functions.
Solution Approach 2:
The patent transitions from planar 2D connections to 3D vertical connections by stacking multiple chips with bonding via holes extending through dielectric layers. This dimensional change enables shorter signal paths and reduced complexity compared to traditional lateral routing, directly improving processing speed while managing connection structure complexity.
2Productivity
If complex connection structures are used, then more connection points are available, but interconnection length increases and performance decreases
Solution Approach 1:
Instead of extending connections laterally across the wafer surface, the patent inverts the connection approach by routing signals vertically through bonding via holes from one chip surface to another. This inversion dramatically reduces interconnection length while maintaining multiple connection points, thereby improving device performance without the penalty of long signal paths.
3Adaptability or versatility
If multiple chips are stacked with complex bonding, then integration increases, but manufacturing complexity increases
Solution Approach 1:
Bonding pads and lead-out pads are pre-formed on chip surfaces before stacking, and bonding via holes are pre-drilled and filled with conductive material in dielectric layers. This preliminary preparation of connection structures simplifies the actual bonding process and reduces manufacturing complexity while enabling high integration through multiple chip stacking.
Solution Approach 2:
The patent uses consistent dielectric materials (such as silicon oxide or silicon nitride) and standardized bonding layer structures across all chip interfaces. This homogeneity in material selection and structural design simplifies the manufacturing process for stacked chips, reducing complexity while maintaining high integration through uniform, repeatable bonding procedures.
Data Source
AI summary
A chip structure, a wafer structure and a method for manufacturing the same are provided in the present disclosure. A first chip and a second chip are bonded by bonding layers of a dielectric material. Top wiring layers are led out through bonding via holes from a back surface of a bonded chip. The bonding via holes are used for bonding and are surrounded by the bonding layers. A top wiring layer of a third chip is led out through bonding pads formed in a bonding layer. The bonding via holes are aligned with and bonded to the bonding pads to achieve bonding of the three chips. The top wiring layer of the third chip is led out from the back surface of the third chip through a lead-out pad.