Chip-to-Chip Interconnects: Vertical PCB Routing for Compact Signal Paths
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Solution Overview
Problem
Conventional chip-to-chip connectors on printed circuit boards require significant physical space, increase production costs, and suffer from signal interference and reduced transmission rates due to incompatible high-speed signals and power circuits.
Innovation Solution
A design using an intermediate printed circuit board positioned between chip substrates and above the main PCB, with pins extending parallel to the main PCB surface to connect chip substrates, and test points for signal quality verification, reducing physical space and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip-to-chip connectors are used on the main PCB, then electrical connection between chip substrates is achieved, but significant physical space is consumed and production costs increase
Solution Approach 1:
The intermediate PCB is positioned vertically above the main PCB, utilizing the third dimension (Z-axis) to relocate the chip-to-chip connection infrastructure. This dimensional transition removes the connection structure from the crowded PCB plane, thereby conserving valuable board space while maintaining electrical connectivity between chip substrates.
Solution Approach 2:
The system is divided into two independent PCB layers: the main PCB for system-level connections and the intermediate PCB for chip-to-chip connections. This segmentation allows each PCB to be optimized for its specific function, reducing the overall space requirement on the main PCB while maintaining reliable electrical connections.
2Reliability
If conventional chip-to-chip connectors are used on the main PCB, then electrical connection between chip substrates is achieved, but production costs increase
Solution Approach 1:
By separating the chip-to-chip connection function onto a dedicated intermediate PCB, the design allows for specialized manufacturing processes optimized for high-speed digital connections. This segmentation enables the use of cost-effective standard PCB fabrication techniques for the intermediate PCB while maintaining high connection reliability, thereby reducing overall production costs compared to integrating all functions into a single complex PCB.
3Speed
If high-speed signals are transmitted through the main PCB, then chip-to-chip communication is enabled, but signal interference occurs due to incompatible power circuits
Solution Approach 1:
The intermediate PCB serves as an intermediary structure between the chip substrates, providing a dedicated pathway for high-speed digital signals. By routing these signals through the intermediate PCB rather than the main PCB, the design isolates them from incompatible power circuits and other interfering elements, thereby maintaining signal integrity and enabling high transmission rates.
Solution Approach 2:
The high-speed signal transmission path is extracted from the main PCB and relocated to the intermediate PCB. This extraction removes the harmful influence of incompatible power circuits and other noise sources from the signal path, allowing high-speed communication to proceed without interference while the main PCB continues to handle power distribution and other functions.
Data Source
AI summary
Electronic modules and methods for manufacturing electronic modules are described herein. Some embodiments of the present invention may be directed to an electronic module that includes a main printed circuit board (PCB) having a first surface, a first chip substrate disposed on the first surface, and a second chip substrate disposed on the first surface. The electronic module may include an intermediate PCB supported by the main PCB, where at least a portion of the intermediate PCB is disposed between the first chip substrate and the second chip substrate. The intermediate PCB may electrically connect the first chip substrate to the second chip substrate. For example, the intermediate PCB may include pins extending substantially parallel to the first surface, and the first chip substrate and the second chip substrate may include contacts configured to electrically connect to the pins of the intermediate PCB.