Chip Structure Vertical Conduction via Interlink Plates
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Solution Overview
Problem
Conventional 3D IC integration techniques, such as through silicon via (TSV), require complex and costly manufacturing processes, including laser perforation and vacuum-based methods, leading to high production costs.
Innovation Solution
A chip structure with vertical electrical conduction using interlink plates and connection terminals that simplify the manufacturing process by eliminating the need for expensive equipment, allowing for chip stacking with a conductive pattern and connection terminals to connect bond and joint pads, thereby facilitating vertical electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D IC integration techniques (TSV) are used, then vertical electrical conduction is achieved, but manufacturing cost increases due to expensive equipment and complex processes
Solution Approach 1:
The invention extracts and eliminates the expensive TSV manufacturing processes (laser perforation, PVD, PECVD) from the chip stacking system. Instead of using through-silicon vias, the patent uses a simplified approach with conductive patterns formed on the chip surface and interlayer insulating layers, removing the need for costly vacuum and dry processing equipment while maintaining vertical electrical conduction functionality
Solution Approach 2:
The invention changes the manufacturing parameters and processes from complex TSV fabrication to simpler conductive pattern formation. The conductive patterns are created using standard semiconductor fabrication techniques without requiring expensive vacuum deposition equipment, thereby reducing manufacturing cost while achieving the same electrical conduction purpose
2Reliability
If conventional TSV processes are used, then vertical connections are established, but device complexity increases due to multiple manufacturing steps
Solution Approach 1:
The invention segments the vertical connection function into separate components: conductive patterns on the chip surface, interlayer insulating layers, and connection terminals. This segmentation allows each component to be formed using simpler, more standardized processes rather than requiring the integrated complex TSV process, reducing overall manufacturing process complexity while maintaining connection reliability
Solution Approach 2:
Instead of creating holes through the silicon substrate (TSV approach), the invention inverts the approach by forming conductive patterns on the surface and using interlayer insulating structures to achieve vertical connections. This inverted methodology simplifies the manufacturing process by avoiding laser perforation and vacuum deposition steps
Data Source
AI summary
A chip structure and a multi-chip stack package are provided. The chip structure includes a chip, at least one interlink plate and a plurality of first connection terminals. The chip has an active surface, a back surface opposite to the active surface and a plurality of side surfaces respectively connected to the active surface and the back surface. The chip includes at least one bond pad disposed on the active surface and at least one joint pad disposed on the back surface. The interlink plate substantially parallel to one of the side surfaces includes a base and a conductive pattern disposed on the base. The conductive pattern is located between the base and the chip. The first connection terminals are disposed between the chip and the interlink plate. The bond pad is electrically connected to the joint pad through the first connection terminals and the conductive pattern.