Semiconductor Chip Mounting Surface Roughness for Thermal Stress Dispersion
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Solution Overview
Problem
Semiconductor devices with power transistors experience solder cracking and delamination due to increased adhesion between the chip mounting portion and the sealing resin, leading to thermal stress issues during temperature cycling tests.
Innovation Solution
Increasing the average surface roughness of the chip mounting portion's surface to 0.8 μm≤Ra≤3.0 μm to disperse thermal stress through large irregularities, preventing solder delamination and maintaining heat dissipation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the adhesion between chip mounting portion and sealing resin is increased, then the sealing performance is improved, but solder cracking and delamination occur during temperature cycling tests
Solution Approach 1:
The patent applies different surface roughness values to different regions of the chip mounting portion. The first region (where solder is applied) has a surface roughness of 0.8 μm≤Ra≤3.0 μm, while the second region (peripheral area) has a different surface roughness. This local differentiation allows the solder region to disperse thermal stress effectively while the peripheral region maintains strong adhesion with the sealing resin, thus preventing solder cracking while ensuring sealing performance.
2Reliability
If the surface roughness of chip mounting portion is increased to disperse thermal stress, then solder cracking is suppressed, but the manufacturing precision requirement increases
Solution Approach 1:
The patent specifies a quantitative range for surface roughness (0.8 μm≤Ra≤3.0 μm) rather than a single value, providing manufacturing flexibility while ensuring effectiveness. This parameter range optimization balances the need for thermal stress dispersion with manufacturability, making it easier to control surface quality during production while still achieving the desired stress dispersion effect.
3Strength
If silica particles are added to solder to improve adhesion, then bonding strength increases, but heat dissipation efficiency decreases
Solution Approach 1:
The patent removes silica particles from the solder composition entirely, using only pure solder material. Instead of relying on silica particles for adhesion, the invention achieves strong bonding and thermal stress dispersion through the optimized surface roughness of the chip mounting portion (0.8 μm≤Ra≤3.0 μm). This extraction of harmful filler materials maintains excellent heat dissipation efficiency while still providing adequate bonding strength through surface engineering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses solder cracking and delamination, enhancing the reliability and heat resistance of semiconductor devices by dispersing thermal stress and eliminating the need for silica particles in the solder, thus reducing manufacturing costs.
Implementation Method 1
it is desired to suppress solder deterioration typified by the occurrence of cracking during a temperature cycling test
Data Source
AI summary
A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is “Ra”, 0.8 μm≤Ra≤3.0 μm holds.