Chip-on-Substrate Packaging Stress Relief via Pre-Cut Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The packaging of integrated circuits faces issues with warpage due to differing Coefficients of Thermal Expansion (CTEs) between device dies and package substrates, leading to irregular joints and bump cracks, which adversely affect the yield of the packaging process.
Innovation Solution
A Chip-on-Substrate package is formed by adhering a wafer-level package substrate on a carrier with a pre-cut, allowing stress release and improved bonding, using a carrier with a lower CTE than the substrate, and bonding dies onto the substrate with a molding material that encapsulates the substrate and dies, facilitating uniform process control and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If organic materials are used for package substrates to enable easy lamination, then ease of manufacture is improved, but warpage occurs due to elevated temperatures during solder reflow
Solution Approach 1:
The patent uses a laminate substrate composed of multiple layers including organic materials and inorganic materials with different CTEs. The inorganic layer (such as glass or ceramic) has lower CTE than the organic layer, compensating for thermal expansion during reflow and reducing warpage while maintaining the lamination capability of organic materials
2Strength
If flip chip bonding is used to bond device dies onto package substrates, then bonding strength is improved, but warpage is worsened due to significantly different CTEs between silicon dies and organic substrates
Solution Approach 1:
The laminate substrate combines organic and inorganic materials where the inorganic layer has CTE matched closer to silicon dies. This composite structure reduces the CTE mismatch between the die and substrate, minimizing warpage during flip chip bonding and reflow while maintaining strong bonding through the solder balls
3Reliability
If elevated temperatures are used for solder reflow to ensure proper bonding, then bonding reliability is improved, but warpage in organic substrates is worsened
Solution Approach 1:
The laminate substrate includes an inorganic layer with low CTE that acts as a thermal stability anchor. During elevated temperature reflow, this layer compensates for the thermal expansion of the organic layer, allowing proper solder bonding to occur while maintaining substrate flatness and preventing warpage
4Stress or pressure
If pre-cut is performed on wafer-level package substrates before bonding, then stress release is improved, but manufacturing complexity is worsened
Solution Approach 1:
The wafer-level substrate is pre-cut into individual package substrates before bonding. This segmentation releases accumulated stress in the substrate and allows each package to be processed independently, improving bonding quality while the modular approach enables parallel processing that offsets the additional step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces stress and improves the reliability of the packaging process by releasing stress in the substrate before bonding, resulting in more uniform and reliable Chip-on-Substrate packages with enhanced adhesion and process control.
Implementation Method 1
since the dies and the package substrates have significantly different Coefficients of Thermal Expansion (CTEs), the warpage in the device dies and the package substrates is worsened
Implementation Method 2
bonding dies onto the substrate with a molding material that encapsulates the substrate and dies
Implementation Method 3
A Chip-on-Substrate package is formed by adhering a wafer-level package substrate on a carrier with a pre-cut
Data Source
AI summary
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.