Chip Package Backside Thermal Vias for Heat Dissipation
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Solution Overview
Problem
Current embedded wafer level ball grid array packages face challenges in achieving effective heat dissipation and cooling without significantly enlarging the chip package.
Innovation Solution
A chip package design where the chip is bonded to a carrier or substrate via the back side, with exposed copper pillars serving as contacts and heat transmission paths to a substrate, and electrical interconnects redirecting contact pads from the front side to solder structures on the back side for both electrical and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If additional electrical and/or heat dissipating structures are provided for heat dissipation, then heat dissipation performance is improved, but chip package size is significantly enlarged
Solution Approach 1:
The patent makes the encapsulation material serve multiple functions: it provides electrical insulation, mechanical protection, and thermal conduction. By selecting encapsulation material with appropriate thermal conductivity (0.2-5.0 W/mK) and forming thermal vias through it, the same structural component handles both insulation and heat dissipation, eliminating the need for separate heat dissipation structures that would increase package size.
Solution Approach 2:
The patent combines the electrical interconnect function and thermal conduction function into the same pathway. The electrical interconnects formed through the encapsulation material also serve as thermal conduction paths, allowing heat to be conducted from the chip to the substrate through the same structures that provide electrical connectivity, thus achieving dual functionality without additional components.
2Temperature
If the chip is bonded to substrate via back side with exposed copper pillars, then heat transmission to substrate is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions during chip fabrication: copper pillars are formed on the chip back side before bonding, and the encapsulation material is applied to expose these pillars. This preliminary preparation ensures that when the chip is bonded to the substrate, the copper pillars are already in position to provide immediate thermal and electrical connectivity, eliminating the need for post-bonding modifications and simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for efficient heat dissipation from the chip to the substrate while maintaining a compact package size, improving thermal management without enlarging the package.
Implementation Method 1
at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side to at least one solder structure formed over a chip package second side
Implementation Method 2
an encapsulation material at least partially surrounding the chip and covering the at least one contact pad
Data Source
AI summary
A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.