Wafer-Level Chip Packaging with Protective Dicing Street Layer

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Solution Overview

Problem

Conventional wafer level chip size packaging methods face issues with metals detaching during electroplating, leading to short circuits, and exposed side surfaces of individual chips being damaged during outer skin packaging, which affects yield and efficiency.

Innovation Solution

A method involving selective forming of a metal electrode using electroplating or vapor deposition, followed by forming a protective layer of thermosetting epoxy resin to cover the dicing street, which protects the metal wires and improves packaging efficiency and yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the wafer is cut into individual chips, then packaging is completed, but the side surfaces of individual chips are exposed and likely to be damaged during outer skin packaging

Engineering Contradiction:
Improvepackaging efficiencyVSAvoidchip integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective layer on the wafer before dicing into individual chips. This protective layer remains on the side surfaces after dicing, providing ongoing protection during outer skin packaging and preventing damage to exposed surfaces, thereby maintaining chip integrity while preserving packaging efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protective layer serves as an intermediary between the chip side surfaces and the external environment during packaging. This intermediary layer prevents direct contact between potential contaminants or mechanical stresses and the vulnerable side surfaces, reducing damage risk without compromising packaging productivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a protective layer is formed to cover the dicing street, then metal detachment is prevented, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvemetal attachment stabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by selecting specific material properties for the protective layer (photosensitive resin with particular characteristics, non-water-soluble resin with specific viscosity range). These parameter optimizations enable the protective layer to provide effective protection while being compatible with standard manufacturing processes, thus maintaining metal attachment stability without excessive process complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses composite materials by combining photosensitive resin and non-water-soluble resin in a multi-layer protective structure. This composite approach provides both adhesion to metal structures and protection during dicing, achieving reliable metal attachment stability while using materials that can be applied with existing manufacturing techniques.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively prevents metal detachment and damage to the side surfaces of individual chips, enhancing packaging efficiency and yield by using a protective layer to cover the dicing street during the wafer dicing process.

Implementation Method 1

selectively forming a metal electrode on the metal pad; the selective forming process may be a selective electroplating process

Methodology Applied
Scientific EffectElectroplating: Electroplating

Implementation Method 2

the selective forming process may be a selective vapor deposition process

Methodology Applied
Scientific EffectVapor deposition: Physical Vapour Deposition

Implementation Method 3

firming a protective layer in area outside the metal electrode on the wafer, the protective layer covering the dicing street

Methodology Applied
Scientific EffectThermal curing: Heat Treatment

Data Source

PatentUS9362173B2Method for chip package
Publication Date: 2016.06.07 NANTONG FUJITSU MICROELECTRONICS
  • US9362173B2 patent drawing
  • US9362173B2 patent drawing
  • US9362173B2 patent drawing

AI summary

Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.