Chip Scale Package Insulation Structure for Exposed Die Reliability

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Solution Overview

Problem

The exposure of semiconductor chip surfaces during the wafer-level chip scale package (WLCSP) process leads to damage and reduced reliability of semiconductor packages due to environmental stress, chemicals, and moisture.

Innovation Solution

A semiconductor package structure is developed with a protective insulating layer covering the semiconductor die's surfaces and a redistribution layer (RDL) structure, along with a passivation layer and conductive structures to provide electrical coupling, encapsulating the RDL and protecting it from environmental damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If WLCSP process is used to reduce package size, then device compactness is improved, but chip surface exposure to environment increases damage risk

Engineering Contradiction:

Improvepackage sizeVSAvoidchip reliability

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent applies a protective insulating layer (mold compound) that encapsulates the chip surfaces and sidewalls, forming a protective shell that shields exposed chip areas from environmental damage while maintaining the compact WLCSP package structure

Inventive Principle:

Principle #30Flexible shells and thin films

Solution Approach 2:

The patent forms a protective insulating layer over the chip surfaces and sidewalls before final package completion, providing beforehand protection against environmental stress, chemicals, and moisture that would otherwise damage the exposed chip areas

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Ease of operation

If chip surfaces are exposed for electrical connections, then electrical connectivity is improved, but susceptibility to environmental damage increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidenvironmental stress

Core Design Contradiction:

Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent applies the protective insulating layer selectively to cover chip surfaces and sidewalls while allowing RDL structures to remain exposed for electrical connections, providing localized protection where needed without compromising electrical connectivity

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The protective insulating layer acts as an intermediary barrier between the chip surfaces and the environment, allowing electrical connections to function while protecting against environmental stress, chemicals, and moisture

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11791266B2Chip scale package structure and method of forming the same

Publication Date: 2023.10.17 MEDIATEK INC

AI summary

A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.