Chip Package Structure with ENIG Plating and Double-Layer Conductive Wires
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Solution Overview
Problem
Current chip package structures, such as CSP, face issues with increased manufacturing complexity, low yield rates, and high costs due to single-layer conductive structures and lack of insulation between bonding pads, leading to reduced use efficiency of wiring space and package size limitations.
Innovation Solution
A chip package structure with a double-layer conductive wire configuration is developed, where multiple dielectric layers are used to form conductive wires and solder points, allowing for improved electrical connections and increased use efficiency of the wiring space on the pad-mounting surface of the die, enhancing precision and yield rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer conductive body structure is used, then the manufacturing process is simpler, but the use efficiency of wiring space is reduced
Solution Approach 1:
The patent transitions from a single-layer conductive structure to a multi-layer conductive structure, adding vertical dimensionality to the wiring arrangement. This allows conductive bodies to be stacked in multiple layers, effectively increasing the wiring space utilization without complicating the fundamental manufacturing approach.
Solution Approach 2:
The conductive structure is segmented into multiple discrete layers, with each layer containing conductive bodies that can be independently formed and positioned. This segmentation enables more efficient use of the available wiring space while maintaining manageable manufacturing complexity through modular construction.
2Ease of manufacture
If no dielectric layer is placed between conductive bodies and pad-mounting surface, then the manufacturing process is simpler, but the insulation effect is negative
Solution Approach 1:
A dielectric layer is introduced as an intermediary substance between the conductive bodies and the pad-mounting surface. This dielectric layer provides the necessary electrical insulation while allowing the manufacturing process to remain relatively simple, as the dielectric can be applied as a continuous coating layer that is then patterned.
3Device complexity
If the conductive body formation step cannot be repeated, then the manufacturing process is simpler, but the use efficiency of wiring space is reduced
Solution Approach 1:
The patent utilizes multiple layers stacked vertically to increase wiring space efficiency. By repeating the conductive body formation step across multiple layers, the design achieves higher density and more efficient space utilization without requiring complex lateral arrangements.
Solution Approach 2:
The dielectric layers are formed in advance to create isolated chambers that define the positions and configurations of conductive bodies in subsequent steps. This preliminary structuring enables efficient space utilization by pre-establishing the spatial framework before conducting the conductive body formation operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double-layer structure effectively increases the use efficiency of the wafer and improves the yield rate of the packaging process by optimizing the use of wiring space and reducing manufacturing costs, while maintaining precision in semiconductor chip packaging.
Implementation Method 1
coat a nickel-gold composite metal layer on the bonding pad and the conductive wire by an electroplating process
Implementation Method 2
coat a metal layer on the bonding pad and the conductive wire by a sputtering process
Implementation Method 3
coat a conductive metal layer on the bonding pad and the conductive wire by a chemical vapor deposition process
Data Source
AI summary
The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.