Chip Package Groove Conductive Layer Stacked Structure
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Solution Overview
Problem
Conventional stacked structures of chip packages face challenges in achieving thinness and high package density due to the thickness of package carrier plates and solder balls, which limits their ability to meet modern design demands for lighter, slimmer, and smaller electronic products.
Innovation Solution
The proposed solution involves a chip package structure with a dielectric layer having grooves on its lateral surfaces, where conductive layers are disposed on the groove walls, and conductive vias are used to connect the chip to the wiring layer, allowing for thinner designs and higher package density by eliminating the need for a conventional package carrier plate and utilizing conductive posts for inter-package connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a conventional package carrier plate structure is used, then the chip package can be assembled and electrically connected, but the thickness of the chip package increases significantly
Solution Approach 1:
The patent removes the conventional package carrier plate from the chip package structure. Instead of using a separate carrier plate substrate, the chip is directly mounted on the lead frame, which serves multiple functions including mechanical support and electrical connection. This extraction of the carrier plate eliminates its thickness contribution to the overall package thickness.
Solution Approach 2:
The patent combines the functions of the package carrier plate and the lead frame into a single integrated structure. The lead frame not only provides electrical connections but also serves as the mechanical support structure that was previously provided by the carrier plate. This merging eliminates the need for a separate carrier plate and reduces overall package thickness.
2Length of moving object
If solder balls with certain height are used for connecting chip packages, then reliable electrical connection is achieved, but the total thickness of stacked structure increases
Solution Approach 1:
The patent extracts and removes the solder balls from the inter-package connection structure. Instead of using spherical solder balls that add significant height, the invention uses flat solder pads on the lead frame that make direct planar contact with adjacent packages, eliminating the vertical dimension contributed by spherical solder joints.
Solution Approach 2:
The patent inverts the conventional connection approach by using a flat planar contact interface instead of a spherical protruding interface. Rather than having solder balls extend vertically from the package surface, the connection is made through flat solder pads that maintain a lower profile while achieving reliable electrical and mechanical connection.
3Productivity
If package carrier plate and chip both have certain thickness, then structural integrity is maintained, but the chip package cannot be thinned for high-density stacking
Solution Approach 1:
The patent merges the carrier plate and lead frame into a single integrated structure where the lead frame provides both mechanical support and electrical connection functions. This integration eliminates the cumulative thickness of separate components while maintaining structural integrity through the lead frame's inherent rigidity and design.
Solution Approach 2:
The patent employs a thin lead frame structure that provides sufficient mechanical support despite reduced thickness. The lead frame is designed with appropriate stiffness and reinforcement features to maintain structural integrity while enabling thin-profile packaging for high-density stacking applications.
Data Source
AI summary
A chip package is provided, which includes a dielectric layer, at least a conductive layer, a chip, a wiring layer and at least a conductive via. The dielectric layer has a first surface, a second surface opposite to the first surface and a plurality of lateral surfaces joined between the first surface and the second surface. One of the lateral surfaces has at least a groove, wherein the groove is extended from the first surface to the second surface. The conductive layer is disposed on the wall of the groove. The chip is inserted in the dielectric layer. The wiring layer is located on the first surface and electrically connected to the conductive layer. The conductive via is located in the dielectric layer to electrically connect the chip to the wiring layer.