Chip Package Substrate Layout for Flexible Heat Dissipation
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Solution Overview
Problem
Conventional heat dissipation sheets in chip packages are inadequate for efficiently managing heat dissipation due to chip miniaturization, leading to potential damage or reduced operational speed.
Innovation Solution
A chip package design with a heat dissipation sheet adhered to a circuit layer via an insulative adhesive, allowing heat to be conducted through conductive sections of the circuit layer, enhancing thermal conductivity and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a conventional heat dissipation sheet is used on a chip, then the chip temperature can be lowered to some extent, but the heat dissipation efficiency is insufficient due to chip miniaturization
Solution Approach 1:
The patent transitions from conventional direct chip-to-heat-sink heat dissipation to a multi-layered thermal management structure that utilizes the substrate circuit layer as an intermediate heat conduction path. The heat dissipation sheet is adhered to the circuit layer through openings in the solder resist layer, creating a three-dimensional thermal conduction pathway that enhances heat dissipation efficiency while accommodating miniaturized chip dimensions.
Solution Approach 2:
The circuit layer serves as an intermediary thermal conduction medium between the chip and the heat dissipation sheet. By adhering the heat dissipation sheet to the circuit layer at specific locations (through the openings), the patent creates an extended thermal management system that effectively dissipates heat from miniaturized chips, overcoming the limitations of conventional direct-contact heat dissipation methods.
2Reliability
If the heat dissipation sheet is adhered directly to the chip, then heat dissipation can be achieved, but the structure lacks flexibility and may cause shear stress
Solution Approach 1:
The patent segments the heat dissipation function by separating the heat dissipation sheet from direct chip contact and instead adhering it to the circuit layer at specific locations. The solder resist layer with its openings creates discrete adhesion points, distributing thermal management functions across multiple locations rather than requiring a continuous rigid connection, thereby enhancing flexibility while maintaining heat dissipation efficiency.
3Reliability
If the circuit layer is fully covered by solder resist layer for protection, then electrical insulation is improved, but heat dissipation capability is reduced
Solution Approach 1:
The patent applies local quality by creating selective openings in the solder resist layer at specific locations where heat dissipation is needed. The solder resist layer remains intact in most areas to provide electrical insulation, while localized openings enable thermal contact between the heat dissipation sheet and the circuit layer, achieving both electrical protection and thermal management simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves heat dissipation efficiency and flexibility, preventing chip damage and maintaining operational speed by increasing contact area with the heat source and reducing shear stress.
Implementation Method 1
the heat dissipation layer is adhered to the second conductive section visible from the second opening via the electrically insulative adhesive, thus, the heat generated by the chip can be conducted to the heat dissipation sheet through the second conductive section
Implementation Method 2
The heat dissipation layer is adhered to the second conductive section visible from the second opening via the electrically insulative adhesive
Data Source
AI summary
A chip package includes a substrate, a chip and a heat dissipation sheet. The substrate includes a carrier, a circuit layer and a solder resist layer. The circuit layer is provided on the carrier, covered by the solder resist layer and has circuit lines. The solder resist layer includes a first opening, a second opening and a covering portion located between the first and second openings. Each of the circuit line has an inner lead, a first conductive section and a second conductive section. The inner lead is visible from the first opening and electrically connected to the chip, the first conductive section is covered by the covering portion, and the second conductive section is visible from the second opening. The heat dissipation sheet is adhered to the second conductive section via an electrically insulative adhesive. Thus, thermal conductivity performance and flexibility of the chip package can be improved.