Chip Package with Interconnected Pins for Signal Delay Reduction
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Solution Overview
Problem
The existing 2D chip packaging process struggles to meet the requirements of high performance, low power consumption, and small size due to difficulties in interconnecting chips, resulting in increased signal delay and larger chip sizes, which do not align with the demands of advanced electronic devices and AI applications.
Innovation Solution
A chip package design featuring a semiconductor substrate with interconnected pins through a connecting layer, allowing for direct interconnection between chips on the same substrate, reducing signal transfer time and enabling high-density packaging by superimposing multiple substrates, thereby meeting the requirements of Moore's Law for performance and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional 2D chip packaging process is used, then chip interconnection is achieved, but signal delay increases and chip size becomes larger
Solution Approach 1:
The patent transitions from traditional 2D chip packaging to a 3D packaging architecture where multiple substrates are stacked vertically. The semiconductor substrate is positioned above the package substrate with chips mounted on the semiconductor substrate, creating vertical interconnections through the connecting layer. This dimensional change reduces signal path length and enables higher density packaging.
Solution Approach 2:
The patent implements a nested structure where the semiconductor substrate with chips is positioned above the package substrate, and the connecting layer is embedded within the semiconductor substrate to provide vertical interconnections. This nested arrangement allows multiple functional layers to be integrated in a compact vertical space, reducing overall package size while maintaining interconnection functionality.
2Quantity of substance
If chip density is increased, then packaging efficiency improves, but interconnection difficulty increases
Solution Approach 1:
By stacking substrates vertically in the third dimension, the patent achieves high chip density without proportionally increasing interconnection complexity. The connecting layer provides systematic vertical interconnection paths through the stacked substrates, making high-density packaging more manufacturable than traditional 2D approaches would allow.
Solution Approach 2:
The patent divides the packaging system into separate functional substrates (package substrate and semiconductor substrate) that can be manufactured and prepared independently, then interconnected through the connecting layer. This segmentation allows for modular manufacturing and assembly, reducing the overall interconnection difficulty compared to creating all interconnections in a single complex process.
3Speed
If signal transfer speed is increased, then performance improves, but energy consumption increases
Solution Approach 1:
The vertical stacking architecture creates shorter signal paths between chips and interconnection points compared to lateral routing in 2D packaging. This reduced path length decreases signal transfer time (increasing speed) while also reducing the energy required for signal transmission, as energy consumption is proportional to path length and resistance.
Data Source
AI summary
The disclosure provides a chip package and an electronic device. The chip package includes: a package substrate, a semiconductor substrate provided on the package substrate and a first chip and a second chip provided on the semiconductor substrate. The semiconductor substrate includes a first group of pins and a second group of pins arranged on the semiconductor substrate and a connecting layer located between the first group of pins and the second group of pins. The connecting layer has a plurality of connecting channels, and the first group of pins and the second group of pins are connected through the plurality of connecting channels. The first chip has a third group of pins, the second chip has a fourth group of pins, and the third group of pins are connected to the first group of pins, and the fourth group of pins are connected to the second group of pins.