Chip Package Interfacial Layer for Conductive Feature Adhesion
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Solution Overview
Problem
New packaging technologies for semiconductor devices face manufacturing challenges due to the need for improved integration density and reduced feature sizes, which affect the reliability and performance of chip packages, particularly in the formation and adhesion of conductive features within these packages.
Innovation Solution
The process involves depositing an adhesive layer and a base layer over a carrier substrate, followed by a seed layer and mask formation to create conductive features, which are then heated to induce grain growth before the formation of a package layer, resulting in conductive features with increased grain size and reduced morphology changes, thereby improving adhesion and interface quality between the conductive features and the package layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If new packaging technologies are adopted to improve integration density, then more components can be integrated into a given area, but manufacturing challenges arise affecting reliability and performance
Solution Approach 1:
The conductive features are heated to induce grain growth before the package layer is formed. This preliminary action ensures that the conductive features have stable, large-grain structures in place before subsequent manufacturing steps, preventing morphology changes and adhesion issues that would compromise reliability in high-density packages.
Solution Approach 2:
The patent changes the thermal parameter by heating the conductive features to specific temperatures that induce grain growth. This parameter change transforms the microstructure of the conductive features, creating larger grains with fewer boundaries, which stabilizes the morphology and improves adhesion in high-density packaging applications.
2Length of moving object
If feature size is reduced to increase integration density, then more components fit in a given area, but adhesion and interface quality of conductive features deteriorate
Solution Approach 1:
By changing the thermal parameter (heating temperature and duration), the patent induces grain growth in the conductive features. This creates larger grains with fewer boundaries, which improves adhesion quality and interface stability even when the overall feature size is reduced for higher integration density.
Solution Approach 2:
The patent creates a composite structure where conductive features with controlled grain structures are integrated with the package layer. The grain-grown conductive features form a more stable interface with the package layer, improving adhesion quality in miniaturized devices.
3Manufacturing precision
If conductive features are formed with smaller grain size, then finer features can be created, but morphology changes and stress/strain increase during subsequent processing
Solution Approach 1:
The conductive features are heated to induce grain growth before the package layer is formed. This preliminary action ensures that the conductive features have stable, large-grain structures in place before subsequent manufacturing steps, preventing morphology changes and adhesion issues that would compromise reliability in high-density packages.
Solution Approach 2:
The patent changes the thermal parameter by heating the conductive features to specific temperatures that induce grain growth. This parameter change transforms the microstructure of the conductive features, creating larger grains with fewer boundaries, which stabilizes the morphology and improves adhesion in high-density packaging applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and performance of chip packages by maintaining the morphologies of conductive features, reducing stress and strain, and improving the interface quality between the package layer and the conductive features, leading to better adhesion and reduced reliability issues.
Implementation Method 1
The conductive feature is heated to induce grain growth to a larger average grain size, where the heating forms an interfacial layer on sidewalls of the conductive feature
Data Source
AI summary
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.


