Structure and formation method for chip package
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Solution Overview
Problem
New packaging technologies for semiconductor devices face manufacturing challenges, particularly in ensuring reliable adhesion and maintaining morphology of conductive features during the formation of chip packages, which affects the reliability and performance of the packages.
Innovation Solution
Conductive features are heated to induce grain growth before the formation of the package layer, reducing stress and strain, and forming interfacial layers to improve the interface quality between the package layer and conductive features, ensuring consistent morphology and enhanced adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive features are formed before package layer formation, then adhesion and morphology reliability are improved, but stress and strain during thermal processes cause morphology changes and interface quality degradation
Solution Approach 1:
The conductive features are formed and stabilized before the package layer formation process begins. By establishing the conductive feature structure in advance and allowing it to settle, the morphology is locked in before subsequent thermal processes occur, preventing stress-induced deformation during package layer formation
Solution Approach 2:
The patent applies a protective coating or interface layer between the conductive features and the package layer to cushion against thermal stress. This protective layer absorbs and distributes the stress during thermal expansion and contraction, preventing direct transmission of stress to the conductive features and maintaining their morphology
2Strength
If thermal processes are applied during package layer formation, then bonding and encapsulation are achieved, but conductive features experience stress-induced morphology changes
Solution Approach 1:
The patent modifies the thermal process parameters (temperature profile, heating rate, holding time) to reduce thermal stress on conductive features. By optimizing these parameters, sufficient bonding strength is achieved while minimizing temperature-induced morphology changes in the conductive features
Solution Approach 2:
An interface layer or undercoat is introduced between the conductive features and the package layer to act as a thermal stress mediator. This intermediary layer has thermal and mechanical properties that buffer the conductive features from direct thermal stress during bonding processes
3Object-affected harmful factors
If package layer is formed over conductive features, then encapsulation and protection are provided, but interface quality deteriorates due to stress and strain
Solution Approach 1:
The patent applies different material properties or structural characteristics at the interface between the package layer and conductive features compared to the bulk package layer. This localized modification creates a stress-relief zone at the critical interface, maintaining high interface quality while providing overall encapsulation protection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and performance of chip packages by maintaining the morphology of conductive features and reducing stress between the package layer and interfacial layers, resulting in improved interface quality and reduced risk of morphology changes during thermal processes.
Implementation Method 1
heating the conductive feature to change the first surface morphology to a second surface morphology, where heating forms an interfacial layer on the sidewalls of the conductive feature
Data Source
AI summary
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.