Chip Package Laser Stop Layer Via Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing fabrication methods for chip packages, such as fingerprint and RF sensors, face challenges in achieving a flat sensing surface, which reduces detection accuracy, and require time-consuming and costly CVD and patterning processes for forming isolation layers.
Innovation Solution
A chip package design that includes a laser stop layer, through holes, an isolation layer, and a conductive layer, where the laser stop layer is used to form a smaller second through hole within a larger first through hole, reducing process time and costs, and improving surface flatness, with a conductive layer that includes a seed and metal layer for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CVD and patterning processes are used to form isolation layer and openings, then manufacturing precision is improved, but loss of time and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the time-consuming CVD and patterning processes from the fabrication flow. Instead of using conventional multi-step processes to form openings through the isolation layer, the invention directly forms conductive vias through the isolation layer using electroplating, eliminating the need for separate CVD deposition and photolithography patterning steps while maintaining manufacturing precision.
Solution Approach 2:
The patent merges the isolation layer formation and via formation processes into a single integrated step. The isolation layer is formed and conductive vias are created simultaneously through electroplating, combining what were traditionally separate CVD and patterning operations into one unified process, thereby reducing total process time while preserving precision.
2Manufacturing precision
If CVD and patterning processes are used to form isolation layer and openings, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates expensive CVD equipment and patterning tooling requirements. By using electroplating to directly form conductive vias through the isolation layer, the invention removes the need for costly CVD deposition equipment, photolithography systems, and associated cleanroom infrastructure, significantly reducing manufacturing capital expenditure and operational costs while maintaining via formation precision.
Solution Approach 2:
The patent employs a sacrificial mandrel structure that is temporarily used during via formation and then removed. This disposable mandrel approach allows for precise via formation through electroplating without requiring expensive reusable patterning masks and photolithography equipment, reducing overall manufacturing cost while maintaining precision.
3Reliability
If conventional fabrication processes are used, then device functionality is achieved, but device size increases
Solution Approach 1:
The patent transitions from planar via formation to vertical via formation through the isolation layer using electroplating. This dimensional change allows for smaller, more compact device layouts by enabling direct vertical connections through the isolation layer without requiring lateral routing through patterned openings, thereby reducing overall device footprint while maintaining electrical connectivity and functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process time and costs, enhances detection accuracy by ensuring a flat sensing surface, and facilitates miniaturization, while eliminating the need for conventional CVD and patterning processes.
Implementation Method 1
A laser is used to remove a portion of the isolation layer to form a second through hole, and the laser is through the first through hole and stopped at the laser stop layer
Data Source
AI summary
A chip package includes a chip, a laser stop layer, a first through hole, an isolation layer, a second through hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first through hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second through hole is extended from the third surface to the first surface, and the second through hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second through hole to contact the laser stop layer.