Chip Package Lateral Openings for Wire Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As chip sizes shrink and the number of conducting pads increases, it becomes difficult to form effective electrical connections due to the challenges of patterning and material deposition in the shrinking holes, leading to increased aspect ratios and reduced accessibility for forming insulating and conducting layers.
Innovation Solution
The proposed chip package design includes a substrate with conducting pads exposed through openings that extend along the side surface, allowing wire layers to contact the pads from the second surface, and a protection layer to prevent damage during dicing, facilitating easier material deposition and reducing the aspect ratio of the openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the chip size is reduced and the number of pads is increased, then the integration density is improved, but the difficulty of forming wires electrically connected to the pads increases
Solution Approach 1:
The patent transitions from traditional vertical hole structures to lateral open channel structures that extend from the side surface of the substrate. This dimensional change allows wire layers to access conducting pads through the side surface rather than through deep vertical holes, significantly reducing the aspect ratio and improving ease of material deposition and wire formation while maintaining high pad density on the chip surface
2Length of stationary object
If the openings are made deeper to expose conducting pads, then the electrical connection is achieved, but the aspect ratio increases and material deposition becomes more difficult
Solution Approach 1:
The patent changes the opening configuration from deep vertical holes to shallow lateral channels that extend from the side surface. This dimensional reconfiguration reduces the aspect ratio of openings while still providing effective access to conducting pads, thereby improving material deposition quality and reducing manufacturing complexity
Solution Approach 2:
The side surface openings act as intermediary pathways that connect the wire layers to the conducting pads without requiring deep penetration into the substrate. These lateral channels serve as intermediate structures that facilitate material deposition and electrical connection while avoiding the problems associated with high aspect ratio vertical holes
Data Source
AI summary
A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.