Chip Package Interfacial Oxide for Via Adhesion Stability

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Solution Overview

Problem

New packaging technologies for semiconductor devices face manufacturing challenges, particularly in ensuring reliable adhesion and maintaining morphology of conductive features during the formation of chip packages, which affects the reliability and performance of the final product.

Innovation Solution

Conductive features are heated to induce grain growth before the formation of the package layer, reducing stress and strain, and an interfacial layer made of metal oxide is formed to improve the interface quality between the conductive features and the package layer, ensuring consistent morphology and enhanced adhesion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conductive features are formed in the package layer, then electrical connectivity is achieved, but stress and strain during package layer formation cause morphology changes and adhesion failures

Engineering Contradiction:
Improveadhesion reliabilityVSAvoidmorphology consistency
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The conductive features are heated to induce grain growth before the package layer is formed. This preliminary action of heating and grain growth preparation stabilizes the conductive features, preventing morphology changes and adhesion failures that would otherwise occur during the stress-inducing package layer formation process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

An interfacial layer is introduced between the conductive features and the package layer. This intermediary layer acts as a buffer that reduces stress and strain transmission during package layer formation, preventing direct adhesion failures at the conductive feature-package layer interface

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If thermal processes are applied during package formation, then package layer curing is achieved, but conductive feature morphology changes occur

Engineering Contradiction:
Improvepackage layer formationVSAvoidconductive feature morphology
Core Design Contradiction:
Ease of manufactureVSShape

Solution Approach 1:

The conductive features are pre-heated to induce complete grain growth before the package layer formation and subsequent thermal processes. This preliminary thermal treatment ensures that the conductive features have already undergone their morphology-changing thermal process, making them resistant to further morphology changes during package layer curing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The heating process changes the physical state and microstructure of the conductive features by inducing grain growth. This parameter change in the conductive features' internal structure stabilizes their morphology, making them resistant to further shape changes during subsequent thermal processes in package formation

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the reliability and performance of chip packages by maintaining the morphologies of conductive features and reducing stress between the package layer and the interfacial layer, resulting in improved interface quality and reduced risk of morphology changes during subsequent thermal processes.

Implementation Method 1

the conductive feature is heated to induce grain growth before the formation of the package layer

Methodology Applied
Scientific EffectGrain growth: Annealing

Data Source

PatentUS9595510B1Structure and formation method for chip package
Publication Date: 2017.03.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9595510B1 patent drawing
  • US9595510B1 patent drawing
  • US9595510B1 patent drawing

AI summary

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.