Chip Package Redistribution Layer Through Substrate Openings
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Solution Overview
Problem
The existing chip packaging process using gold wires and lead frames is costly and increases the size of the chip package, making it difficult to further miniaturize the package.
Innovation Solution
A chip package is formed using a first substrate with micro-electric elements and conducting pads, where a second substrate is disposed on top, covered by an encapsulation layer, and a redistribution layer extends through openings in the substrate to electrically connect the pads, replacing traditional wire and lead frame connections with through silicon vias, ring-contacts, or T-contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold wires and lead frames are used for electrical connections, then reliable electrical connection paths are achieved, but the package size increases and manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the lead frame from the packaging structure, retaining only the essential electrical connection function through substrate-integrated pads and vias. This removes the bulky lead frame component while maintaining electrical connectivity through redesigned substrate pathways.
Solution Approach 2:
The patent merges the electrical connection function directly into the substrate structure by integrating conducting pads and vias within the substrate itself, rather than using separate lead frames and wire bonds. This consolidation eliminates additional components and reduces overall package volume.
2Reliability
If gold wires and lead frames are used for electrical connections, then reliable electrical connection paths are achieved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive gold wires with cheaper alternative materials for electrical connections. The substrate-integrated conducting paths use cost-effective materials and processes, eliminating the need for precious metal wire bonding while maintaining functional reliability.
Solution Approach 2:
The patent extracts and eliminates the expensive lead frame component from the assembly, replacing it with substrate-integrated electrical pathways. This removal of the lead frame significantly reduces material costs and simplifies the manufacturing process.
3Reliability
If traditional wire and lead frame connections are used, then electrical connectivity is achieved, but device complexity increases
Solution Approach 1:
The patent merges multiple separate components (lead frame, wire bonds, bonding pads) into a single integrated substrate structure with embedded conducting pathways. This consolidation simplifies the overall device architecture by reducing the number of discrete parts and assembly steps.
Solution Approach 2:
The patent extracts and removes the complex wire bonding and lead frame assembly process, replacing it with simpler substrate-integrated electrical pathways that are formed during substrate fabrication, thereby reducing structural complexity.
Data Source
AI summary
A chip package including a first substrate having a first surface and a second surface opposite thereto is provided. The first substrate has a micro-electric element and a plurality of conducting pads adjacent to the first surface. The first substrate has a plurality of openings respectively exposing a portion of each conducting pad. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conducting pads.