Chip Package Formation Using Release Film to Protect Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
New packaging technologies for semiconductor devices face manufacturing challenges due to the need for improved integration density and functionality, which are not adequately addressed by existing methods.
Innovation Solution
A chip package formation process involving the bonding of chip structures with different heights over a substrate, using a release film to prevent the package layer from covering the top surfaces of the chip structures and avoiding planarization processes to enhance reliability and quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If planarization process is used to flatten the package surface, then the package layer can be formed uniformly, but the chip structures may be damaged and reliability decreases
Solution Approach 1:
The patent applies preliminary action by forming the package layer to a specific thickness before removing the release film, ensuring the package layer is sufficiently formed to protect the chip structures during subsequent processing. This preliminary formation of the package layer with controlled thickness prevents damage to chip structures while achieving uniform coverage.
Solution Approach 2:
The patent changes the parameter of package layer thickness from being determined by planarization (which removes material) to being determined by controlled deposition thickness (which adds material). By controlling the deposition thickness to be greater than the release film thickness, the package layer maintains uniformity without requiring damaging planarization steps.
2Ease of operation
If release film is removed completely, then the top surfaces of chip structures are exposed for bonding, but the package layer may cover and damage the chip structures
Solution Approach 1:
The patent performs preliminary action by forming the package layer to a thickness greater than the release film thickness before removing the release film. This ensures that when the release film is removed, the package layer remains in place to protect the chip structures, eliminating the need for delicate alignment during release film removal.
Solution Approach 2:
The patent applies beforehand cushioning by creating an excess thickness of package layer that serves as a protective cushion. This extra package layer material acts as a buffer that prevents direct contact between subsequent processing steps and the chip structures, protecting them from damage while allowing easy access for bonding operations.
3Reliability
If package layer thickness is increased to cover taller chip structures, then all chip structures are protected, but the package becomes larger and more complex
Solution Approach 1:
The patent changes the parameter control from post-formation thickness adjustment (planarization) to pre-formation thickness control (deposition thickness). By setting the deposition thickness parameter to be greater than the release film thickness, the package layer uniformly covers all chip structures of different heights without requiring additional material removal, optimizing both protection and size.
Data Source
AI summary
Formation methods of a chip package are provided. The method includes bonding a first chip structure and a second chip structure over a substrate. The method also includes forming a release film to cover top surfaces of the first chip structure and the second chip structure. The method further includes forming a package layer to surround the first chip structure and the second chip structure after the formation of the release film. In addition, the method includes removing the release film such that the top surface of the first chip structure, the top surface of the second chip structure, and a top surface of the package layer are exposed.