Chip Package Stepped Sidewall and Tapered Adhesive for Singulation
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Solution Overview
Problem
The increasing complexity of chip packaging manufacturing poses challenges such as support capability for the cover glass, device defects during the singulation process, and filling capability of the encapsulant layer, necessitating novel chip packages and methods that address these issues.
Innovation Solution
A chip package design featuring a substrate with stepped sidewalls, a capping layer, a dam structure, and an adhesive layer with a concave-tapered sidewall, along with a method involving bonding, dicing, and debonding processes to form a chip package that improves mechanical support and encapsulant layer filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a conventional chip packaging process is used, then the manufacturing process is simpler, but the support capability for the cover glass is insufficient
Solution Approach 1:
The substrate is divided into a first substrate and a second substrate that are bonded together to form a stacked structure. This segmentation provides enhanced mechanical support for the cover glass while maintaining manufacturing feasibility through sequential processing steps.
Solution Approach 2:
The first substrate is prepared with a recess region and the second substrate is prepared in advance before bonding. This preliminary preparation ensures proper alignment and support capability, allowing the cover glass to be effectively supported after assembly.
2Reliability
If a conventional singulation process is used, then the device complexity is lower, but device defects occur during the singulation process
Solution Approach 1:
The singulation process is divided into two separate dicing operations: a first dicing process that creates initial separation lines, and a second dicing process that completes the separation. This segmented approach reduces defects by avoiding the need for a single complex high-stress cutting operation.
Solution Approach 2:
The first dicing process is performed in advance to create preliminary separation lines, and the second dicing process is performed after bonding to complete the separation. This preliminary action allows for controlled separation that minimizes device defects during singulation.
3Manufacturing precision
If a conventional encapsulant layer filling process is used, then the manufacturing process is simpler, but the filling capability of the encapsulant layer is insufficient
Solution Approach 1:
The recess region in the first substrate is designed with an asymmetric shape that creates a tapered filling path for the encapsulant layer. This asymmetric geometry guides the encapsulant material to flow and fill the encapsulation space completely, improving filling capability.
Solution Approach 2:
The recess region features curved surfaces that facilitate smooth flow of the encapsulant layer during filling. The curved geometry prevents air entrapment and ensures complete filling of the encapsulation space, enhancing manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the mechanical support and filling capability of the encapsulant layer, reducing defects and improving the reliability of the chip package by aligning interfaces and forming a rounded angle with the adhesive layer, thereby addressing the challenges in chip packaging.
Implementation Method 1
an adhesive layer bonding the capping layer to the substrate
Implementation Method 2
The encapsulant layer has a rounded angle in direct contact with the adhesive layer
Data Source
AI summary
Chip packages and methods for forming the same are provided. The chip package includes a substrate having a stepped sidewall, a first surface, and a second surface. The first surface and the second surface are opposite each other. The first surface and the second surface adjoin the stepped sidewall. The chip package also includes a capping layer having a first surface and a second surface opposite each other. The first surface of the capping layer faces the second surface of the substrate. The chip package further includes a dam structure and an adhesive layer. The dam structure bonds the capping layer to the substrate, and surrounds a sensing region in the substrate. The adhesive layer surrounds the dam structure and has a concave-tapered sidewall that extends along the outer edge of the dam structure in the direction from the second surface of the substrate to the capping layer.