Wafer-Level Chip Package Spacer Layer Adhesion
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Solution Overview
Problem
In wafer-level packaging, chip packages in the periphery region of the wafer often suffer from poor adhesion and moisture infiltration, affecting the reliability of the packaged chip.
Innovation Solution
A manufacturing method involving a semiconductor wafer with a spacer layer and a package substrate, where through holes in the spacer layer are filled with an adhesive material different from the spacer layer material, enhancing adhesion and preventing delamination during the packaging process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a spacer layer is used to define cavities in wafer-level packaging, then the device region is exposed and protected, but the periphery region suffers from poor adhesion and moisture infiltration
Solution Approach 1:
The spacer layer is segmented by forming through-holes that divide it into separate adhesive regions. Different adhesive materials can be applied to different segments (periphery vs. device region), allowing optimized adhesion solutions for each area. This segmentation enables the periphery to have enhanced adhesion without compromising the device region exposure.
Solution Approach 2:
Different adhesive materials with different properties are applied to different locations: a first adhesive material is applied to the periphery region through-holes for strong bonding and moisture barrier, while a second adhesive material is applied to the device region for compatible adhesion. This local quality approach ensures each region gets the optimal adhesive properties for its specific function.
2Strength
If adhesive material is applied to the periphery region, then adhesion is improved, but the complexity of the manufacturing process increases
Solution Approach 1:
The through-holes are formed in the spacer layer before applying the adhesive materials. This preliminary action creates pre-defined pathways and regions for adhesive application, making the subsequent adhesive application process more controlled and less complex. The structure is prepared in advance to facilitate the adhesion enhancement step.
Solution Approach 2:
The through-holes act as intermediaries that facilitate the application of adhesive materials to the periphery region. Instead of applying adhesive directly to the complex periphery area, the through-holes provide simple, defined channels for adhesive delivery, reducing the complexity of the application process while ensuring proper adhesion.
3Ease of manufacture
If the same adhesive material is used throughout, then the manufacturing process is simplified, but adhesion performance varies in different regions
Solution Approach 1:
Different adhesive materials are applied to different regions: the periphery region receives a first adhesive material optimized for bonding and moisture resistance, while the device region receives a second adhesive material optimized for device compatibility. This local differentiation ensures consistent adhesion performance across all regions despite the added material variety.
Solution Approach 2:
The adhesive application process is segmented into distinct regions through the through-hole structure. The periphery through-holes receive one adhesive material while the device region receives another, allowing each segment to have optimized adhesion properties. This segmentation maintains manufacturing simplicity by using clear spatial separation rather than complex application procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves the adhesion between the semiconductor wafer, package substrate, and spacer layer, enhancing the yield and reliability of the chip packaging process by preventing delamination during thermal and chemical processes.
Implementation Method 1
filling an adhesive material in the through holes wherein a material of the spacer layer is adhesive and different from the adhesive material
Data Source
AI summary
An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.


