Wafer-Level Chip Package With Spacer Layer
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Solution Overview
Problem
The conventional chip packaging process is complex and lacks a simplified method for forming chip packages without adhesion glue, which complicates the protection and connection of chips in electronic products.
Innovation Solution
A chip package is formed using a wafer-level packaging process that includes a semiconductor substrate with a dielectric layer and conducting pad structures, a cover substrate, and a spacer layer that creates cavities without adhesion glue between the chip and the spacer layer, allowing for direct contact and simplified dicing into separated packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip packaging process is used, then chips are protected and connection is provided, but the process becomes complicated
Solution Approach 1:
The patent merges the spacer layer and adhesion glue into a single integrated layer. The spacer layer is formed to directly contact both the chip and cover substrate, eliminating the need for a separate adhesion glue layer. This integration simplifies the packaging process while maintaining reliable chip protection and electrical connection through the conducting pad structures.
Solution Approach 2:
The patent extracts and eliminates the adhesion glue component from the packaging structure. By designing the spacer layer to directly contact the chip without requiring adhesion glue, the process complexity is reduced while the essential functions of spacing, protection, and electrical connection are preserved through the integrated spacer and conducting pad design.
2Strength
If adhesion glue is used between chip and spacer layer, then bonding is achieved, but fabrication time and cost increase
Solution Approach 1:
The spacer layer is designed to directly contact the chip without requiring a separate adhesion glue layer. This integration eliminates the additional fabrication steps and materials needed for adhesion glue application, reducing both fabrication time and cost while maintaining the necessary bonding strength through the direct contact design.
3Reliability
If conventional packaging process is used, then chip protection is provided, but size and cost of package increase
Solution Approach 1:
The packaging process is segmented into wafer-level processing followed by dicing. Multiple chips are packaged simultaneously on the wafer, and the wafer is diced into individual packages after the packaging structure is formed. This segmentation enables mass production efficiency, reducing the overall package size and cost while maintaining effective chip protection through the integrated spacer and cover substrate design.
Data Source
AI summary
Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer.