Chip Package Structure With Spacer Via Structures

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Multi-chip package structures face issues with increased thickness and higher electrical resistance due to vertical stacking, leading to increased power consumption.

Innovation Solution

A chip package structure that includes a circuit board, a first die, a spacer with via structures, and a second die, where the second die is electrically connected to the circuit board through the spacer, effectively shortening the bonding wire length and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If chips are vertically stacked to reduce package area, then the area of the package structure is reduced, but the thickness of the package structure becomes excessively high

Engineering Contradiction:

Improvepackage structure areaVSAvoidpackage structure thickness

Core Design Contradiction:

Area of stationary objectVSLength of stationary object

Solution Approach 1:

The patent transitions from vertical stacking (z-dimension) to horizontal arrangement with spacers (x-y plane), changing the dimensional approach to achieve area reduction without excessive thickness increase

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple spacers are nested between the circuit board and the second die, creating a compact horizontal structure that reduces overall package area while maintaining controlled thickness

Inventive Principle:

Principle #7Nested doll (Nesting)

2Area of stationary object

If chips are vertically stacked to reduce package area, then the area of the package structure is reduced, but the resistance of electrical path from the top chip to the circuit board becomes larger

Engineering Contradiction:

Improvepackage structure areaVSAvoidelectrical resistance

Core Design Contradiction:

Area of stationary objectVSLoss of energy

Solution Approach 1:

Conductive spacers serve as intermediary elements between the second die and the circuit board, providing direct electrical connection paths that reduce resistance compared to long bonding wires

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The electrical connection path is segmented into multiple conductive elements (spacer conductors, via structures) rather than relying on a single long bonding wire, reducing overall resistance

Inventive Principle:

Principle #1Segmentation

3Area of stationary object

If chips are vertically stacked to reduce package area, then the area of the package structure is reduced, but power consumption increases due to larger resistance

Engineering Contradiction:

Improvepackage structure areaVSAvoidpower consumption

Core Design Contradiction:

Area of stationary objectVSUse of energy by moving object

Solution Approach 1:

Conductive spacers act as intermediary connection elements that provide low-resistance electrical paths, reducing power consumption compared to traditional long bonding wire connections

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the electrical connection parameter from long bonding wires to short spacer-based conductive paths, fundamentally altering the resistance and power consumption characteristics of the package

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11133291B2Chip package structure with multi-chip stack

Publication Date: 2021.09.28 POWERTECH TECHNOLOGY INC

AI summary

A chip package structure including a circuit board, a first die, a spacer, and a second die. The first die is disposed on the circuit board, and the spacer is disposed on the circuit board, in which the spacer includes a spacer part and at least one via structure penetrating through the spacer part. The second die is disposed on the first die and the spacer, and the second die is electrically connected to the circuit board through the spacer.