Chip Packaging Structure for Warpage and Heat Dissipation
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Solution Overview
Problem
Existing chip packaging technologies face issues of increased chip warpage and low heat dissipation efficiency due to thermal expansion coefficient mismatches and rising power demands.
Innovation Solution
A chip packaging structure and method involving a temporary substrate with a separation layer, rewiring layers, conductive posts, and a heat sink element, along with symmetrically placed dummy wafers to reduce thermal expansion mismatch and establish heat dissipation channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If no further thinning is performed for large-size thick silicon chips, then chip warpage increases sharply due to thermal expansion coefficient mismatch, but chip thickness is maintained
Solution Approach 1:
The patent introduces a carrier substrate as an intermediary carrier to support the thick silicon chip during packaging processes. The carrier substrate has thermal expansion coefficients matched to reduce warpage, and provides mechanical support to maintain chip flatness without requiring thinning of the chip itself.
Solution Approach 2:
The patent changes the thermal expansion parameters by selecting carrier substrate materials with thermal expansion coefficients that match both the silicon chip and the packaging substrate, thereby reducing thermal stress and warpage during temperature variations in the packaging process.
2Productivity
If multiple chips are packaged in the same package structure, then packaging integration is improved, but heat dissipation efficiency decreases due to heat source formation
Solution Approach 1:
The patent segments the heat dissipation pathways by providing individual heat dissipation structures for each chip package unit. Each chip has its own heat dissipation channel that extends to the carrier substrate, allowing heat from multiple chips to be dissipated independently rather than accumulating in a shared structure.
Solution Approach 2:
The patent extends heat dissipation from a two-dimensional plane to a three-dimensional structure by incorporating vertical heat dissipation channels through the carrier substrate. The heat dissipation structures extend in the thickness direction, providing additional dimensional pathways for heat removal while maintaining horizontal packaging integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces chip warpage and enhances heat dissipation efficiency by mitigating thermal expansion coefficient mismatches and establishing efficient heat transfer pathways.
Implementation Method 1
bonding a heat sink element to the second chip
Implementation Method 2
forming a laminate layer, and the laminate layer covering the conductive post and the first chip
Data Source
AI summary
The chip package structure and a method are disclosed, comprising: a substrate, a first rewiring layer, a first chip, a dummy wafer, a laminate layer, a second rewiring layer, a second chip, a metal connection through-hole, and a heat dissipation element. By introducing a dummy wafer with a lower thermal expansion coefficient on both sides of the first chip, the mismatch of the thermal expansion coefficient of the encapsulation structure can be reduced, and the warping generated by the chip during the encapsulation process can be reduced. By forming a metal connecting post between the first chip and the second chip, a heat dissipation passage is established to further reduce the encapsulation thermal resistance and thus improve the heat dissipation efficiency of the chip, so as to form a chip encapsulation structure with a better heat dissipation performance by combining heat dissipation elements.