Chip Power Consumption Analysis with Early Bump Current Prediction
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Solution Overview
Problem
Conventional chip power consumption analysis during the post-layout stage is inefficient, making it difficult to adjust bump current sources, leading to prolonged design cycles and reduced efficiency.
Innovation Solution
A chip power consumption analyzer and analysis method that predicts bump current demand and peak currents during the early design stage by calculating clock arriving times, setting a base cell type, and establishing demand current information, allowing for optimization of power supply design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If power consumption analysis is performed during the post-layout stage, then analysis accuracy is improved, but design cycle time is prolonged and adjustment flexibility is reduced
Solution Approach 1:
The patent performs power consumption analysis during the pre-layout stage by calculating clock arriving times and predicting demand peak currents of bump current sources before physical design is completed. This preliminary action allows designers to identify and address power consumption issues early in the design process, avoiding the need for time-consuming post-layout analysis and iterations.
Solution Approach 2:
The patent introduces an intermediary analysis method that uses clock arriving times and demand current information as intermediate parameters to predict power consumption characteristics. This intermediary approach provides sufficient accuracy for early-stage decision-making without requiring the computational resources and time of full post-layout analysis.
2Adaptability or versatility
If bump current sources are added, removed, or changed during post-layout stage, then power consumption optimization is improved, but implementation difficulty increases and time consumption increases
Solution Approach 1:
The patent predicts demand peak currents and identifies optimal bump current source configurations during the pre-layout stage, allowing designers to make configuration decisions before physical design is finalized. This preliminary determination makes subsequent implementation straightforward and avoids complex modifications during post-layout stage.
3Measurement precision
If detailed power consumption analysis is performed during post-layout stage, then analysis accuracy is improved, but design efficiency is reduced
Solution Approach 1:
The patent performs power consumption analysis during the pre-layout stage by calculating clock arriving times and predicting demand peak currents before physical design is completed. This preliminary action allows designers to identify and address power consumption issues early in the design process, avoiding the need for time-consuming post-layout analysis and iterations.
Solution Approach 2:
The patent changes the analysis parameters from detailed post-layout electrical simulations to pre-layout calculations based on clock arriving times and demand current information. This parameter change enables sufficiently accurate power consumption estimation with significantly reduced computational requirements and faster execution time.
Data Source
AI summary
Disclosed are a chip power consumption analyzer and an analyzation method thereof. The analyzation method includes the following. Design information of a circuit is received. A plurality of clock arriving times of a plurality of circuit cells in the circuit are calculated based on the design information, and a base cell type is set among a plurality of cell types according to the clock arriving times. Base demand current information of the base cell type is established, and a plurality of demand current information of the circuit cells is obtained. A plurality of demand peak currents of a plurality of bump current sources are predicted according to the demand current information and a plurality of position information of the circuit cells.