On-Chip Power-Glitch Detector With Autonomous Self-Test
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Solution Overview
Problem
Existing systems-on-chip (SoC) designs lack effective methods to detect and self-test for power-glitch attacks, which are sophisticated hacking techniques that compromise chip security.
Innovation Solution
A chip with integrated power-glitch detection and self-testing capabilities, utilizing a processor, glitch detector, and self-testing circuit, which includes a glitch generator and controller, operates internally without requiring additional test pads, using a phase-locked loop for sharp glitch signals and multiplexers for mode switching, and includes feedback mechanisms for error verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional external testing methods are used for glitch detectors, then testing can be performed, but additional test pads and external equipment are required, increasing device complexity and reducing reliability
Solution Approach 1:
The patent merges the testing function with the glitch detector by integrating a self-testing circuit directly into the glitch detector module. The self-testing circuit includes a glitch generator, pulse generator, and D-flip flops that are all contained within the same detector structure, eliminating the need for external test pads and equipment. This integration resolves the contradiction by improving reliability through built-in testing while reducing device complexity.
Solution Approach 2:
The glitch detector performs self-testing through its integrated self-testing circuit that generates test glitch signals internally and verifies its own operation. The circuit uses internal components (glitch generator, pulse generator, D-flip flops) to autonomously test the detector's rising and falling edge responses without requiring external service or equipment, thus improving reliability while simplifying the overall testing structure.
2Measurement precision
If comprehensive glitch detection coverage is achieved, then detection accuracy improves, but the circuit complexity increases
Solution Approach 1:
The patent segments the glitch detection function into distinct operational modes (rising edge detection, falling edge detection, and self-testing mode) implemented through separate circuit paths within the detector. The self-testing circuit uses individual components (glitch generator, pulse generator, D-flip flops) for each testing function, allowing comprehensive coverage while maintaining organized, modular circuit structure that manages complexity.
Solution Approach 2:
The glitch detector is designed with multi-functionality to handle both normal glitch detection and self-testing operations through a unified circuit structure. The same detector circuitry serves dual purposes: detecting external glitch signals during normal operation and receiving internally generated test signals during self-testing mode, thereby achieving comprehensive detection coverage without proportionally increasing circuit complexity.
Data Source
AI summary
Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector.