Chip Redistribution Structure With Staggered RDL Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor manufacturing technologies face limitations in improving the redistribution density of redistribution layers (RDLs) on chip surfaces due to process constraints, leading to reduced integration density and increased risk of short circuits.
Innovation Solution
A chip redistribution structure is proposed, featuring a dielectric layer with recessed windows and a groove, where the first and second distribution layers are disposed in a staggered manner along the height direction, reducing the horizontal gap between them. Both layers are made of the same material and are formed on a metal seed layer, simplifying the process and improving density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a multi-layer distribution mode is adopted to improve redistribution density, then the redistribution density can be improved, but the process complexity increases due to additional metal seed layer preparation and etching steps
Solution Approach 1:
The patent merges the metal seed layer preparation step into a single common step that serves both the first and second distribution layers. Instead of preparing separate metal seed layers for each layer, a single metal seed layer is prepared on the dielectric layer, and both distribution layers are formed on this common seed layer, thereby reducing process complexity while maintaining high redistribution density
Solution Approach 2:
The patent segments the distribution structure into multiple layers (first distribution layer and second distribution layer) positioned at different heights, with the first distribution layer extending along the groove and the second distribution layer disposed above the dielectric layer. This segmentation allows high redistribution density to be achieved while using a simplified common seed layer preparation process
2Manufacturing precision
If the line size of RDL and gap between different RDLs are reduced to improve density, then the redistribution density improves, but the process capability limitation prevents further reduction
Solution Approach 1:
The patent transitions from a single-plane distribution structure to a multi-height layer structure. The first distribution layer is positioned at a lower height extending along the groove, while the second distribution layer is positioned at a higher height above the dielectric layer. This three-dimensional arrangement increases redistribution density without requiring further reduction of line size or gaps within a single plane, thereby overcoming process capability limitations
3Manufacturing precision
If multiple distribution layers are prepared with separate metal seed layers, then each layer can be independently optimized, but the risk of short circuit increases due to excess metal removal by etching
Solution Approach 1:
The patent combines the metal seed layer preparation into a single common step for both distribution layers. By preparing one metal seed layer that serves both the first and second distribution layers, the number of etching operations is reduced, thereby minimizing the risk of short circuits while still allowing independent optimization of each distribution layer's pattern and dimensions
Data Source
AI summary
The present invention provides a chip redistribution structure and a preparation method thereof. The chip redistribution structure includes a chip body, and a first distribution layer and a second distribution layer which are connected to the chip body. A first pin and a second pin are disposed on the surface of the chip body. The chip redistribution structure further includes a dielectric layer disposed on the surface of the chip body, wherein the dielectric layer is recessed downwards to form a first window, a second window, and a groove interconnected with the first window. The first window and the second window respectively correspond to the first pin and the second pin. The first distribution layer extends along the groove and is interconnected with the first pin, and the second distribution layer is disposed above the dielectric layer and is interconnected with the second pin.