Chip Power-On Reset Timing Using Pulse-Based Measurement

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing power-on reset circuits integrated into processor chips face challenges in accurately measuring power-on reset time, leading to long verification times and low efficiency.

Innovation Solution

A method and system that detect the power supply pin voltage and output signal of a chip to record specific time points, allowing for the accurate computation of power-on reset time using the formula T(P) = (T2 - T1) - (T3 - T2), where T1 is the first time point, T2 is the second time point, and T3 is the third time point, and optionally correcting the reset time using the reset trigger time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a maximum power-on reset time is set for verification, then verification can be completed, but the verification time becomes long and efficiency becomes low

Engineering Contradiction:

Improvepower-on reset circuit verificationVSAvoidverification time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces manual timing measurement methods with an automated detection system that uses a detection device to automatically capture voltage signals and output signals, computing the power-on reset time through programmed logic rather than mechanical timing procedures

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The detection device automatically detects and records the necessary time points (when power supply voltage reaches preset voltage, when first pulse output completes, when second pulse output completes) without requiring external manual intervention, enabling self-measurement of the power-on reset time

Inventive Principle:

Principle #25Self-service

2Productivity

If accurate power-on reset time measurement is implemented, then verification efficiency improves, but measurement precision requirements increase

Engineering Contradiction:

Improveverification efficiencyVSAvoidpower-on reset time measurement precision

Core Design Contradiction:

ProductivityVSMeasurement precision

Solution Approach 1:

The system uses feedback by detecting the output signal of the preset pin and using its pulse outputs as indicators to determine when the power-on reset process has completed specific stages, allowing precise calculation of the reset time based on measurable event markers

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The detection device is pre-configured to detect and record the specific time points needed for calculation before the actual power-on reset measurement begins, ensuring that all necessary data is captured with appropriate precision for the subsequent computation

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11287453B2Method and system for measuring power-on reset time

Publication Date: 2022.03.29 SHENZHEN GOODIX TECH CO LTD

AI summary

A method for measuring a power-on reset time includes: detecting a power supply pin voltage of a chip, and recording a time point at which the power supply pin voltage reaches a preset voltage as a first time point; detecting an output signal of a preset pin of the chip, and recording a time point at which the preset pin completes a pulse output for a first time after the chip is powered on, as a second time point, and recording a time point the preset pin completes a pulse output for a second time, as a third time point; wherein widths of the pulse output for the first time and for the second time are the same; and computing the power-on reset time of the chip according to the first time point, the second time point and the third time point.