Chip Resistor Offset Electrodes Heat Dissipation
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Solution Overview
Problem
Conventional chip resistors face challenges in heat dissipation efficiency due to small electrode sizes, which hinder effective heat dissipation despite increased resistance requirements.
Innovation Solution
A chip resistor design featuring a resistor board with offset electrodes, an insulating layer, and specific plating layers to enhance heat dissipation, including a first underlying layer and a plating layer with Cu, Ag, or Au inner films and Sn outer films, and a second underlying layer and plating layer with Ni intermediate films, all formed by sputtering to ensure efficient thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between the two electrodes is increased to achieve high resistance, then the resistance increases, but the electrode size becomes small which reduces heat dissipation efficiency
Solution Approach 1:
The patent introduces a multi-layer structure with underlying layers, plating layers, and insulating layers arranged in different dimensions. The underlying layer extends in the planar direction while the plating layer provides vertical thickness, creating a three-dimensional electrode structure that increases heat dissipation surface area without increasing the footprint distance between electrodes
Solution Approach 2:
The electrode is constructed as a composite structure with different material layers: the underlying layer (e.g., Cu, Ag, Al) provides electrical conductivity and heat dissipation, while the plating layer (e.g., Sn, Ni, Pd) provides protection and solderability. This composite structure enables simultaneous optimization of electrical performance and thermal management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves heat dissipation efficiency by allowing for larger plating layers and underlying layers, maintaining resistance while efficiently dissipating heat, thus addressing the limitations of conventional chip resistors.
Implementation Method 1
The first underlying layer is formed by sputtering
Data Source
AI summary
A chip resistor includes a resistor board, a first electrode, a second electrode and an insulating layer. The second electrode is offset from the first electrode in a lateral direction perpendicular to the thickness direction of the resistor board. The obverse surface of the resistor board includes a first region in contact with the first electrode, a second region in contact with the second electrode and an intermediate region in contact with the insulating layer. The intermediate region is disposed between the first region and the second region in the lateral direction. The first electrode includes a first underlying layer and a first plating layer. The first underlying layer is disposed between the first plating layer and the insulating layer in the thickness direction of the resistor board.