Chip Scale Package Composite Board Embedding
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Solution Overview
Problem
Conventional chip scale packages face issues with electrical connection quality due to chip deviation, encapsulant overflow, and warpage caused by adhesive film softening during the package molding process, leading to poor electrical connections and increased fabrication costs.
Innovation Solution
A fabrication method using a composite board with a hard layer and a soft layer, where the chip is embedded in the soft layer and supported by a hard layer, allowing for a redistribution layer process without the need for an additional hard carrier, thereby preventing chip deviation and warpage and ensuring reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a chip is attached to an adhesive film for package molding, then the chip can be fixed during the molding process, but the adhesive film softens and extends due to heat causing chip deviation and poor electrical connection
Solution Approach 1:
The patent divides the support structure into two distinct layers: a soft layer (first layer) that provides cushioning and stress absorption, and a hard layer (second layer) that provides rigid support and dimensional stability. This segmentation allows each layer to perform its specific function without interfering with the other, preventing chip deviation while maintaining electrical connection reliability.
Solution Approach 2:
The patent employs a composite board structure combining a soft layer and a hard layer with different mechanical properties. The soft layer (e.g., polyimide) provides flexibility and stress distribution, while the hard layer (e.g., ceramic or metal) provides rigidity and thermal stability. This composite structure resolves the contradiction by providing both chip fixation and heat resistance to prevent adhesive film softening and chip deviation.
2Ease of manufacture
If the adhesive film is used to support multiple chips, then chip mounting is simplified, but warpage occurs in the adhesive film and encapsulant leading to uneven dielectric layer formation
Solution Approach 1:
The support structure is segmented into a soft layer for chip mounting and a hard layer for warpage prevention. The hard layer provides a rigid backbone that prevents the entire structure from warping during molding, while the soft layer maintains its ability to accommodate chip placement. This ensures uniform dielectric layer formation during the RDL process.
Solution Approach 2:
The composite board with soft and hard layers combines the advantages of both material types: the soft layer provides ease of chip mounting and stress absorption, while the hard layer provides warpage resistance. This composite structure maintains manufacturing precision by preventing encapsulant overflow and ensuring flat surfaces for dielectric layer deposition.
3Stability of the object's composition
If a hard carrier is used to prevent warpage, then the encapsulant can be secured, but adhesive residue remains on the encapsulant after the carrier is removed
Solution Approach 1:
The hard layer is permanently integrated into the composite board structure before chip mounting, eliminating the need for separate carrier attachment and removal operations. This preliminary integration prevents adhesive residue contamination while maintaining encapsulant flatness throughout the manufacturing process.
Solution Approach 2:
The hard layer is merged with the soft layer to form an integrated composite board structure. This unified structure provides both warpage prevention and chip support functions without requiring separate carriers, thereby eliminating the source of adhesive residue contamination while maintaining encapsulant stability.
4Volume of moving object
If the chip size is reduced for high integration, then compactness is improved, but the surface area for mounting solder balls is insufficient
Solution Approach 1:
The patent extends the solder ball mounting area from the chip surface to the composite board surface. By forming the built-up layer and solder balls on the composite board rather than directly on the chip, the mounting area is effectively expanded in the planar dimension without increasing chip size, enabling high integration while providing sufficient solder ball capacity.
Solution Approach 2:
The composite board acts as an intermediary between the chip and the external connection structure. The soft layer and hard layer provide a platform for forming the built-up layer and solder balls, decoupling the chip size from the solder ball mounting area. This allows small chips to be mounted on a larger composite board structure that provides adequate connection capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability of electrical connections, reduces the risk of encapsulant overflow, and eliminates the need for additional carriers, resulting in improved product yield and reduced fabrication costs by maintaining the chip's position and preventing adhesive residue.
Implementation Method 1
a soft layer having opposite first and second surfaces... the first surface of the soft layer is bonded to the adhesive layer such that the chip is embedded in the soft layer
Implementation Method 2
providing a carrier board having an adhesive layer... disposing the chip on the adhesive layer via the active surface thereof
Data Source
AI summary
A fabrication method of a chip scale package includes: disposing a chip on a carrier board and embedding the chip into a composite board having a hard layer and a soft layer; and removing the carrier board so as to perform a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, chip deviation and contamination, etc., all of which may result in poor electrical connection between the wiring layer and the chip electrode pads in the subsequent RDL process and even waste products as a result.