Chip Scale Package With Inorganic Insulating Coating
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Solution Overview
Problem
Traditional plastic semiconductor packages are unsuitable for space-restricted applications due to their thickness and the risk of short circuits between semiconductor die contacts and the solder pads during mounting, leading to potential device failure from unwanted electrical contact and leakage currents.
Innovation Solution
A semiconductor chip scale package with inorganic insulating material, such as aluminum oxide (Al2O3) or alternating layers of Al2O3 and TiO2, applied to the side walls and major surfaces of the semiconductor die using atomic layer deposition or low-temperature PECVD, ensuring electrical isolation and protection without covering the electrical contacts, allowing direct surface mounting on a carrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If traditional plastic packaging is used to encapsulate semiconductor dies, then the dies are protected against damage, but the package thickness becomes too large (10 μm to several 100 μm) for space-restricted applications
Solution Approach 1:
The patent replaces traditional thick plastic epoxy molding compound with a thin film ceramic coating applied directly to the semiconductor die. This ceramic layer provides the necessary mechanical protection and environmental sealing while maintaining a thickness of only a few micrometers, enabling chip-scale packaging that meets space-restricted application requirements.
2Volume of stationary object
If the semiconductor die surfaces and side walls are left unprotected to achieve chip scale package size, then the package volume is nearly identical to the die volume, but the unprotected surfaces create short circuit risks between contacts and solder pads during mounting
Solution Approach 1:
The patent applies insulating ceramic material selectively to specific regions of the semiconductor die - covering the side walls and upper surfaces while leaving the solder pad contact areas exposed. This localized application provides electrical isolation where needed to prevent short circuits during mounting, while maintaining direct contact between the solder pads and mounting board for proper electrical connection.
Solution Approach 2:
The ceramic coating acts as an intermediary insulating layer between the semiconductor die and the mounting environment. It provides electrical isolation and environmental protection for the die surfaces and side walls, while the exposed solder pads serve as intermediaries for making controlled electrical connections to the mounting board without unwanted current paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides enhanced electrical isolation, mechanical protection, and hermeticity while maintaining the package volume identical to the die, preventing unwanted current paths and ensuring reliable device performance in space-constrained environments.
Implementation Method 1
applied to the side walls and major surfaces of the semiconductor die using atomic layer deposition
Implementation Method 2
applied to the side walls and major surfaces of the semiconductor die using atomic layer deposition or low-temperature PECVD
Data Source
AI summary
The disclosure relates to chips scale packages and methods of forming such packages or an array of such packages. The semiconductor chip scale package comprises: a semiconductor die, comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an inorganic insulating material arranged on the plurality of side walls and on the first major surface.