Chip Scale Package Wafer-Level EMI Shielding
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Solution Overview
Problem
Conventional chip scale package structures are limited in thickness and width due to bonding wire constraints, cannot be directly shipped in wafer level form, and lack electromagnetic interference (EMI) protection, making them vulnerable to external electronic component disturbances.
Innovation Solution
A chip scale package structure comprising a chip, dam unit, board body, conductors, encapsulating glue, conductive layers, isolation layer, and electrodes, where the conductors and conductive layers are electrically connected and encapsulated, allowing for reduced size and EMI protection through a shielding layer, enabling direct wafer level shipping and protection of internal components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If bonding wire is used to connect chips to external circuit contacts, then electrical connection is achieved, but the thickness and width of the package structure are limited by the available wiring area
Solution Approach 1:
The patent extracts the bonding wire from the package structure by implementing wafer-level packaging where connections are established before dicing. The wire bonds are confined to the wafer level and do not extend into the final packaged product, effectively removing the wiring area constraint from the package thickness and width dimensions.
Solution Approach 2:
The patent transitions from three-dimensional wire bonding within the package to two-dimensional planar connections at the wafer level. By establishing all electrical connections before dicing, the package structure can be reduced in thickness without being constrained by wire routing requirements.
2Productivity
If conventional chip scale package structure is manufactured, then chip packaging is achieved, but the structure cannot be directly shipped in wafer level package
Solution Approach 1:
The patent performs all packaging operations including wire bonding, encapsulation, and conductor attachment at the wafer level before dicing. This preliminary action allows the entire wafer to be packaged simultaneously, enabling direct shipping in wafer form and eliminating the need for individual chip packaging operations after dicing.
3Reliability
If conventional chip scale package structure is used, then chip encapsulation is achieved, but the structure is absent from electromagnetic interference (EMI) preventing element
Solution Approach 1:
The patent merges the EMI shielding function with the existing package structure by integrating a shielding layer into the encapsulating glue or substrate. This combination approach provides EMI protection without adding separate shielding components, maintaining reliability while controlling device complexity.
Data Source
AI summary
A chip scale package structure includes a chip, a dam unit, a board body, a plurality of first conductors, an encapsulating glue, a plurality of first conductive layers, an isolation layer, and a plurality of first electrodes. The dam unit is disposed on the surface of the chip. The board body is located on the dam unit. The first conductors are respectively in electrical contact with the conductive pads of the chip. The encapsulating glue covers the surface of the chip, and the board body and the first conductors are packaged in the encapsulating glue. The first conductive layers are located on the surface of the encapsulating glue opposite to the chip and respectively in electrical contact with the first conductors. The isolation layer is located on the encapsulating glue and the first conductive layers. The first electrodes are respectively in electrical contact with the first conductive layers.