Chip Scan Chain Testing with Integrated Encoding and Decoding Circuits
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Solution Overview
Problem
Conventional chip testing methods require expensive automatic testing machines and struggle to differentiate between digital logic defects and scan mode entry failures, making it difficult to identify error sources within the chip.
Innovation Solution
A chip with integrated scan chains, encoding circuits, and decoding circuits that output testing sequences and determine errors in scan output data, allowing for direct scan chain testing and reducing the need for expensive automatic testing machines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional chip testing method using automatic testing machine is used, then error coverage rate is improved, but testing cost increases
Solution Approach 1:
The chip performs self-testing by generating test sequences internally through the encoding circuit and automatically analyzing results through the decoding circuit, eliminating the need for expensive external automatic testing machines while maintaining effective error detection capabilities
2Measurement precision
If conventional scan mode testing is used, then error detection capability is improved, but ability to identify error source is worsened
Solution Approach 1:
The testing system is segmented into distinct functional modules: encoding circuit for generating test sequences, scan chains for error propagation, and decoding circuit for result analysis. This segmentation enables identification of where errors occur in the testing process itself, distinguishing between digital logic defects and scan mode entry failures
Solution Approach 2:
The decoding circuit receives scan output data and provides feedback about test results, enabling determination of whether errors exist and facilitating identification of error sources by analyzing the relationship between input test sequences and output results
Data Source
AI summary
A chip testing method including the following operations is disclosed: outputting a plurality of testing sequences to a plurality of scan chains by an encoding circuit; generating a plurality of scan output data according to the plurality of testing sequences by the plurality of scan chains; and determining whether an error exists in the plurality of scan chains or not according to the plurality of scan output data by a decoding circuit.